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參數(shù)資料
| 型號： | SI5020 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC |
| 中文描述： | SiPHY多速率SONET / SDH的時鐘和數(shù)據(jù)恢復芯片 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大?。?/td> | 335K |
| 代理商： | SI5020 |
Preliminary Rev. 0.8 12/00
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Copyright 2000 by Silicon Laboratories
Si5020-DS08
Si5020
SiPHY M
ULTI
-R
ATE
SONET/SDH C
LOCK
AND
D
ATA
R
ECOVERY
IC
Features
Complete high speed, low power, CDR solution includes the following:
Applications
Description
The Si5020 is a fully integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-48/12/3, STM-16/4/1,
or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data streams is also
provided for OC-48/STM-16 applications that employ forward error
correction (FEC). DSPLL technology eliminates sensitive noise entry
points thus making the PLL less susceptible to board-level interaction and
helping to ensure optimal jitter performance.
The Si5020 represents a new standard in low jitter, low power, and small
size for high speed CDRs. It operates from a single 2.5 V supply over the
industrial temperature range (–40°C to 85°C).
Functional Block Diagram
!
Supports OC-48/12/3, STM-16/4/1,
Gigabit Ethernet, and 2.7 Gbps FEC
!
Low Power—270 mW (TYP OC-48)
!
Small Footprint: 4 mm x 4 mm
!
DSPLL Eliminates External Loop
Filter Components
!
3.3 V Tolerant Control Inputs
!
Exceeds All SONET/SDH
Jitter Specifications
Jitter Generation
3.0 mUI
RMS
(TYP)
Device Power Down
Loss-of-Lock Indicator
Single 2.5 V Supply
!
!
!
!
!
SONET/SDH/ATM Routers
!
Add/Drop Multiplexers
!
Digital Cross Connects
!
Gigabit Ethernet Interfaces
!
SONET/SDH Test Equipment
Optical Transceiver Modules
SONET/SDH Regenerators
Board Level Serial Links
!
!
!
BUF
BUF
DSPLL
Phase-Locked
Loop
Retimer
LOL
2
2
DIN+
DIN–
BUF
REFCLK+
REFCLK–
2
PWRDN/CAL
2
RATESEL1–0
2
CLKOUT+
CLKOUT–
DOUT+
DOUT–
REXT
Bias
Ordering Information:
See page 14.
Pin Assignments
Si5020
1
2
3
4
5
6
7
8
9
13
14
15
16
REXT
VDD
GND
REFCLK+
REFCLK–
PWRDN/CAL
VDD
DOUT+
DOUT–
VDD
12
11
10
GND
Pad
17
18
19
20
R
R
G
C
C
L
V
G
D
D
Top View
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