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參數(shù)資料
| 型號： | SI5017-D-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECOVERY 28MLP |
| 標準包裝： | 60 |
| 系列： | DSPLL® |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | SONET/SDH，ATM 應(yīng)用 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-MLP-EP（5x5） |
| 包裝： | 管件 |
| 其它名稱： | 336-1279 |
Si5017
Rev. 1.5
21
22
23
CLKOUT–
CLKOUT+
OCML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN except when LTR is asserted or the
LOL state has been entered.
24
CLKDSBL
I
LVTTL
Clock Disable.
When this input is high, the CLKOUT output drivers
are disabled. For normal operation, this pin should
be low.
Note: This input has a weak internal pulldown.
26
BER_LVL
I
Bit Error Rate Level Control.
The BER threshold level is set by applying a volt-
age to this pin. When the BER exceeds the pro-
grammed threshold, BER_ALM is driven low. If this
pin is tied to GND, BER_ALM is disabled.
27
BER_ALM
OLVTTL
Bit Error Rate Alarm.
This pin will be driven low to indicate that the BER
threshold set by BER_LVL has been exceeded.
There is no hysteresis.
28
NC
No Connect.
Leave this pin disconnected.
GND Pad
GND
Supply Ground.
Nominally 0.0 V. The GND pad found on the bottom
of the 28-lead QFN (see Figure 16 on page 23)
must be connected
directly to supply ground.
Minimize the ground path inductance for optimal
performance.
Table 8. Si5017 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5018-B-GM | IC CLOCK/DATA RECOVERY 20-QFN |
| SI5020-B-GM | IC CLK DATA REC SONET/SDH 20-QFN |
| SI5023-D-GM | IC CLOCK/DATA RECVRY W/AMP 28MLP |
| SI52142-A01AGM | IC CLK GENERATOR 200MHZ 24QFN |
| SI52143-A01AGM | IC CLK GEN QUAD PCIE 24QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5017-D-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 OC48/STM16 CDR FEC RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5017-EVB | 功能描述:時鐘和定時器開發(fā)工具 OC48 STM16 SNT/SDH 2.7Gbps w/ limit amp RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5017-X-GM | 制造商:SILABS 制造商全稱:SILABS 功能描述:OC-48/STM-16 SONET/SDH CDR IC WITH LIMITING AMPLIFIER |
| SI5018 | 制造商:SILABS 制造商全稱:SILABS 功能描述:SiPHY⑩ OC-48/STM-16 CLOCK AND DATA RECOVERY IC WITH FEC |
| SI-50182 | 制造商:BEL 制造商全稱:Bel Fuse Inc. 功能描述:SI-50182 |
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