參數(shù)資料
型號: SI4020-I1-FT
廠商: Silicon Laboratories Inc
文件頁數(shù): 25/32頁
文件大?。?/td> 1058K
描述: IC TX FSK 915MHZ 5.4V 16-TSSOP
標(biāo)準(zhǔn)包裝: 96
頻率: 315MHz,433MHz,868MHz,和 915MHz
調(diào)制或協(xié)議: FSK,OOK
數(shù)據(jù)傳輸率 - 最大: 256 kbps
電流 - 傳輸: 14mA
數(shù)據(jù)接口: PCB,表面貼裝
天線連接器: PCB,表面貼裝
電源電壓: 2.2 V ~ 5.4 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 585 (CN2011-ZH PDF)
其它名稱: 336-1621-5
Si4020
 
 
25
 
Sensitive Reset Enabled, Ripple on V
dd
:
time
V
dd
Reset threshold voltage
(600mV)
nRes
output
H
L
1.6V
Reset ramp line
(100mV/ms)
 
Sensitive reset disabled:
time
V
dd
Reset threshold voltage
(600mV)
nRes
output
H
L
250mV
Reset ramp line
(100mV/ms)
 
Software reset
Software reset can be issued by sending the appropriate control command (described at the end of the section) to the chip. The
result of the command is the same as if power-on reset was occurred.
Vdd line filtering
During the reset event (caused by power-on, fast positive spike on the supply line or software reset command) it is very important to
keep the Vdd line as smooth as possible. Noise or periodic disturbing signal superimposed the supply voltage may prevent the part
getting out from reset state. To avoid this phenomenon use adequate filtering on the power supply line to keep the level of the
disturbing signal below 10mVp-p in the DC  50kHz range for 200ms from Vdd ramp start.. Typical example when a switch-mode
regulator is used to supply the radio, switching noise may be present on the Vdd line. Follow the manufacturers recommendations
how to decrease the ripple of the regulator IC and/or how to shift the switching frequency.
Related control commands
Low Battery Detector Command
Setting bit<6> to high will change the reset mode to normal from the default sensitive.
SW Reset Command
Issuing FF00h command will trigger software reset. See the Wake-up Timer Command.
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