參數(shù)資料
型號(hào): SI4020-I1-FT
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 12/32頁(yè)
文件大小: 1058K
描述: IC TX FSK 915MHZ 5.4V 16-TSSOP
標(biāo)準(zhǔn)包裝: 96
頻率: 315MHz,433MHz,868MHz,和 915MHz
調(diào)制或協(xié)議: FSK,OOK
數(shù)據(jù)傳輸率 - 最大: 256 kbps
電流 - 傳輸: 14mA
數(shù)據(jù)接口: PCB,表面貼裝
天線連接器: PCB,表面貼裝
電源電壓: 2.2 V ~ 5.4 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 585 (CN2011-ZH PDF)
其它名稱: 336-1621-5
Si4020
 
 
12
 
CONTROL INTERFACE
Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on
pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits
sent is an integer multiple of 8. All commands consist of a command code, followed by a varying number of parameter or data bits.
All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no influence (dont care) are indicated with X. The Power
On Reset (POR) circuit sets default values in all control and command registers.
Timing Specification
 
 
 
 
 
 
Timing Diagram
SCK
SDI
nIRQ
nSEL
t
DS
t
DH
t
CH
t
CL
BIT15
BIT14
BIT13
t
SS
POR
BIT8
BIT7
t
OD
WK-UP
nIRQ
BIT1
BIT0
t
SH
t
SHI
 
 
Symbol
Parameter
Minimum value [ns]
t
CH
 
Clock high time
25
t
CL
 
Clock low time
25
t
SS
 
Select setup time (nSEL falling edge to SCK rising edge)
10
t
SH
 
Select hold time (SCK falling edge to nSEL rising edge)
10
t
SHI
 
Select high time
25
t
DS
 
Data setup time (SDI transition to SCK rising edge)
5
t
DH
 
Data hold time (SCK rising edge to SDI transition)
5
t
OD
 
Data delay time
10
t
BL
 
Push-button input low time
25
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