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| 型號： | Si3232-X-GQ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DUAL PROGRAMMABLE CMOS SLIC WITH LINE MONITORING |
| 中文描述： | 兩個可編程的CMOS用戶接口與在線監(jiān)測 |
| 文件頁數(shù)： | 25/128頁 |
| 文件大?。?/td> | 2327K |
| 代理商： | SI3232-X-GQ |
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Si3232
Preliminary Rev. 0.96
25
4.4. Linefeed Calibration
An internal calibration algorithm corrects for internal and
external component errors. The calibration is initiated by
setting the CAL register bit. Upon completion of the
calibration cycle, this bit is automatically reset.
It is recommended that a calibration be executed
following system powerup. Upon release of the chip
reset, the device is in the Open state, and calibration
can be initiated. Only one calibration should be
necessary as long as the system remains powered up.
The Dual ProSLIC calibration sequence consists of
SLIC mode calibration, monitor ADC calibration, and
audio path calibration. The calibration bits that are set in
registers CALR1 and CALR2 are executed in order of
MSB to LSB for each sequential register. CALR1, bit 7
starts the calibration sequence. CALR2 calibration bits
should be set before the CALR1 is written. The reserved
bit (bit 6) of CALR1 must always be cleared to 0. The
interrupt bit, bit 7 of IRQ3, will report an error in the
calibration process. The error could include the line
becoming off-hook during the common mode balance
calibration.
During all calibrations, the calibration engine controls
VTIP and VRING to provide the correct external voltage
conditions for the calibration algorithm. The TIP and
RING leads must not be connected to ground during
any calibration.
The leakage calibrations (CALR1, bits 4–5) can be done
at regular intervals to provide optimal performance over
temperature
variations.
calibrations can be performed every hour. Invoke these
leakage calibrations, only during on-hook, by setting
The
TIP/RING
leakage
CALR1 to 0xB0. The leakage calibration takes 5 ms and
interferes with dc feed and voice transmission during its
process.
4.4.1. Common Mode Calibration
To optimize common mode (longitudinal) balance
performance, it is recommended that the user perform
the following steps when running the common-mode
calibration routine:
1. Write the Register values as shown in Table 15.
These coefficient values select a 600
impedance
synthesis
2. Set Common Mode Balance Interrupt
(IRQEN3 = 0x80)
3. Set CALR2 = 0x01. This enables only the AC
longitudinal balance calibration routine (CALCMBAL)
4. Set CALR2 = 0x80. This begins the calibration
process.
5. Wait for the CALR1 register to clear to 0x0,
indicating the longitudinal balance calibration is
complete (up to 100ms).
6. Ensure that a common mode balance error interrupt
did not occur. Retry calibration if true.
7. Rewrite desired register values that were changed
during this calibration.
During all calibrations, the calibration engine controls
VTIP and VRING to provide the correct external voltage
conditions for the calibration algorithm. The TIP and
RING leads must not be connected to ground during
any calibration. Note that the channel being calibrated
must be on-hook.
Table 14. Register and RAM Locations used for Loop Monitoring
Parameter
Register/RAM
Mnemonic
VLOOP
Register/
RAM Bits
VLOOP[15:0]
Measurement Range
LSB Size
Effective
Resolution
251 mV
628 mV
251 mV
628 mV
251 mV
628 mV
500
μ
A*
500
μ
A*
Loop Voltage Sense
(V
TIP
– V
RING
)
TIP Voltage Sense
0 to 64.07 V
64.07 to 160.173 V
0 to 64.07 V
64.07 V to 160.173 V
0 to 64.07 V
64.07 V to 160.173 mA
0 to 101.09 mA
0 to 101.09 mA
4.907 mV
VTIP
VTIP[15:0]
4.907 mV
RING Voltage Sense
VRING
VRING[15:0]
4.907 mV
Loop Current Sense
Longitudinal Current
Sense
Battery Voltage Sense
ILOOP
ILONG
ILOOP[15:0]
ILONG[15:0]
3.907
μ
A
3.907
μ
A
VBAT
VBAT[15:0]
0 to 64.07 V
64.07 to 160.173 V
4.907 mV
251 mV
628 mV
*Note:
I
LOOP
and I
LONG
are calculated values based on measured I
Q1
–I
Q4
currents. The resulting effective resolution is
approximately 500
μ
A.
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