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參數(shù)資料
| 型號： | SI3225PPTX-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 92/112頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL W/DISCRETE INTERFACE |
| 設計資源： | Si3225PPTX-EVB Schematics/Layout |
| 標準包裝： | 1 |
| 系列： | ProSLIC® |
| 主要目的： | 接口，模擬前端（AFE） |
| 已用 IC / 零件： | Si3225 |
| 已供物品： | 板，CD |
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Si3220/25 Si3200/02
80
Rev. 1.3
Not
Recommended
fo
r N
ew
D
esi
gn
s
Figure 52. Example, Timeslot 1, Long FSYNC (TXS/RXS = 0)
Figure 53. Example, IDL2 Long FSYNC, B2, 10-Bit Mode (TXS/RXS = 10)
3.30. PCM Companding
The Dual ProSLIC devices support both -255 Law (-
Law) and A-Law companding formats in addition to
Linear Data mode. The data format is selected via the
PCMF bits of the PCM Mode Select register. -Law
mode is more commonly used in North America and
Japan, and A-Law is primarily used in Europe and other
countries. These 8-bit companding schemes follow a
segmented curve formatted as a sign bit (MSB) followed
by three chord bits and four step bits. A-Law typically
uses a scheme of inverting all even bits while -Law
does not. Dual ProSLIC devices also support A-Law
with inversion of even bits, inversion of all bits, or no bit
inversion by programming the ALAW bits of the PCM
Mode Select register to the appropriate setting.
Table 43 on page 82 and Table 44 on page 83 define
the -Law and A-Law encoding formats.
The Dual ProSLIC devices also support a 16-bit linear
data format with no companding. This Linear mode is
typically used in systems that convert to another
companding format, such as adaptive differential PCM
(ADPCM) or systems that perform all companding in an
external DSP. The data format is 2s complement with
MSB first (sign bit). Transmitting and receiving data via
Linear mode requires two continuous time slots. An 8-bit
Linear
mode
enables
8-bit
transmission
without
companding.
01
7
6
5
4
3
2
16
15
14
13
12
11
10
9
818
17
MSB
LSB
MSB
LSB
HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
01
7
6
5
4
3
2
16
15
14
13
12
11
10
9
818
17
MSB
LSB
MSB
LSB
HI-Z
PCLK
FSYNC
PCLK_CNT
DRX
DTX
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