參數(shù)資料
型號(hào)： SI3210-KT
廠(chǎng)商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 89/148頁(yè)
文件大?。?/td> 0K
描述： IC PROSLIC W/DC-DC CONV 38TSSOP
標(biāo)準(zhǔn)包裝： 50
系列： ProSLIC®
功能： 用戶(hù)線(xiàn)路接口概念（SLIC），CODEC
接口： PCM，SPI
電路數(shù)： 1
電源電壓： 3.3V，5V
電流 - 電源： 88mA
功率（瓦特）： 700mW
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 38-TFSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 38-TSSOP
包裝： 管件
包括： BORSCHT 功能，DTMF 生成和解碼，F(xiàn)SK 生成，脈沖測(cè)量生成，語(yǔ)音回送測(cè)試模式
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Si3210/Si3211
Rev. 1.61
45
Not
Recommended
fo
r N
ew
D
esi
gn
s
In addition, the user must select the sinusoidal ringing
waveform by writing TSWS = 0 (direct Register 34,
bit 0).
2.4.3. Trapezoidal Ringing
In addition to the sinusoidal ringing waveform, the
ProSLIC
supports
trapezoidal
ringing.
illustrates a trapezoidal ringing waveform with offset
VROFF.
Figure 22. Trapezoidal Ringing Waveform
To configure the ProSLIC for trapezoidal ringing, the
user should follow the same basic procedure as in the
Sinusoidal Ringing section, but using the following
equations:
RCO is a value added or subtracted from the waveform
to ramp the signal up or down in a linear fashion. This
value is a function of rise time, period, and amplitude,
where rise time and period are related through the
following equation for the crest factor of a trapezoidal
waveform.
where T = ringing period, and CF = desired crest factor.
For example, to generate a 71 VPK, 20 Hz ringing
signal, the equations are as follows:
For a crest factor of 1.3 and a period of 0.05 seconds
(20 Hz), the rise time requirement is 0.0153 seconds.
In addition, the user must select the trapezoidal ringing
waveform by writing TSWS = 1 in direct Register 34.
2.4.4. Ringing DC voltage Offset
A dc offset can be added to the ac ringing waveform by
defining
the
offset
voltage
in
ROFF
(indirect
Register 19). The offset, VROFF, is added to the ringing
signal when RVO is set to 1 (direct Register 34, bit 1).
The value of ROFF is calculated as follows:
2.4.5. Linefeed Considerations During Ringing
Care must be taken to keep the generated ringing signal
within the ringing voltage rails (GNDA and VBAT) to
maintain
proper
biasing
of
the
external
bipolar
transistors. If the ringing signal nears the rails, a
distorted ringing signal and excessive power dissipation
in the external transistors results.
To prevent this invalid operation, set the VBATH value
(direct Register 74) to a value higher than the maximum
peak ringing voltage. The discussion below outlines the
considerations and equations that govern the selection
of the VBATH setting for a particular desired peak ringing
voltage.
First, the required amount of ringing overhead voltage,
VOVR, is calculated based on the maximum value of
current through the load, ILOAD,PK, the minimum current
gain of Q5 and Q6, and a reasonable voltage required
to keep Q5 and Q6 out of saturation. For ringing signals
up to VPK =87V, VOVR = 7.5 V is a safe value.
However, to determine VOVR for a specific case, use the
equations below.
RCO
0.99211
2
15
32509
7EFDh
==
=
RNGX
1
4
---
0.00789
1.99211
---------------------
2
15
70
96
------
376
0177h
=
RNGY
0
=
time
VROFF
T=1/freq
tRISE
VTIP-RING
RNGY
1
2
---
Period
8000
=
RNGX
Desired V
PK
96 V
-----------------------------------
2
15
=
RCO
2
RNGX
t
RISE
8000
---------------------------------
=
t
RISE
3
4
---T1
1
CF
2
-----------
–
=
RNGY 20 Hz
1
2
---
1
20 Hz
----------------
8000
200
C8h
=
RNGX 71 V
PK
71
96
------
2
15
24235
5EABh
=
RCO 20 Hz, 1.3 crest factor
2
24235
0.0153
8000
--------------------------------------
396
018Ch
=
ROFF
V
ROFF
96
------------------
2
15
=
I
LOAD,PK
V
AC,PK
R
LOAD
-------------------
I
OS
+
V
AC,PK
N
REN
6.9 k
------------------
I
OS
+
==
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