參數(shù)資料
型號(hào)： SI3019-F-FS
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 48/94頁(yè)
文件大?。?/td> 0K
描述： IC LINE-SIDE DAA 16SOIC
標(biāo)準(zhǔn)包裝： 48
系列： ISOcap™
數(shù)據(jù)格式： V.92
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 管件
Si3056
Si3018/19/10
52
Rev. 1.05
Reset settings = 0000_0000
Register 4. Interrupt Source
Bit
D7D6D5
D4D3D2
D1
D0
Name
RDTI
ROVI
FDTI
BTDI
DODI
LCSOI
DLCSI
POLI
Type
R/W
Bit
Name
Function
7RDTI
Ring Detect Interrupt.
0 = A ring signal is not occurring.
1 = A ring signal is detected. If the RDTM (Register 3) and INTE (Register 2) bits are set a hard-
ware interrupt occurs on the AOUT/INT pin. This bit must be written to a 0 to be cleared. The RDI
bit (Register 2) determines if this bit is set only at the beginning of a ring pulse, or at the end of a
ring pulse as well. This bit should be cleared after clearing the PDL bit (Register 6) because pow-
ering up the line-side device may cause this interrupt to be triggered.
6ROVI
Receive Overload Interrupt.
0 = An excessive input level on the receive pin is not occurring.
1 = An excessive input level on the receive pin is detected. If the ROVM and INTE bits are set a
hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to clear it. This bit is
identical in function to the ROV bit (Register 17). Clearing this bit also clears the ROV bit.
5FDTI
Frame Detect Interrupt
.
0 = Frame detect is established on the communications link.
1 = This bit is set when the communications link does not have frame lock. If the FDTM and INTE
bits are set, a hardware interrupt occurs on the AOUT/INT pin. Once set, this bit must be written
to a 0 to be cleared.
4BTDI
Billing Tone Detect Interrupt.
0 = A billing tone has not occurred.
1 = A billing tone has been detected. If the BTDM and INTE bits are set, a hardware interrupt
occurs on the AOUT/INT pin. This bit must be written to 0 to clear it.
3DODI
Drop Out Detect Interrupt
.
0 = The line-side power supply has not collapsed.
1 = The line-side power supply has collapsed (The DOD bit in Register 19 has fired). If the
DODM and INTE bits are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be
written to 0 to be cleared. This bit should be cleared after clearing the PDL bit (Register 6)
because powering as the line-side device can cause this interrupt to be triggered.
2LCSOI
Loop Current Sense Overload Interrupt
.
0 = The LCS bits have not reached max value (all ones).
1 = The LCS bits have reached max value. If the LCSOM bit (Register 3) and the INTE bit are
set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to 0 to be cleared.
LCSOI does not necessarily imply that an overcurrent situation has occurred. An overcurrent sit-
uation in the DAA is determined by the status of the OPD bit (Register 19). After the LCSOI inter-
rupt fires, the OPD bit should be checked to determine if an overcurrent situation exists.
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