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參數(shù)資料
| 型號： | SI3019-F-FS |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 20/94頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE-SIDE DAA 16SOIC |
| 標準包裝： | 48 |
| 系列： | ISOcap™ |
| 數(shù)據(jù)格式： | V.92 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC N |
| 包裝： | 管件 |
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Si3056
Si3018/19/10
Rev. 1.05
27
Several events occur in the DAA when the OFHK pin is
asserted or the OH bit is set. There is a 250
s latency
to allow the off-hook command to be communicated to
the line-side device. Once the line-side device goes off-
hook, an off-hook counter forces a delay for line
transients to settle before transmission or reception
occurs. This off-hook counter time is controlled by the
FOH[1:0] bits (Register 31, bits 6:5). The default setting
for the off-hook counter time is 128 ms, but can be
adjusted up to 512 ms or down to either 64 or 8 ms.
After the off-hook counter has expired, a resistor
calibration is performed for 17 ms. This allows circuitry
internal to the DAA to adjust to the exact conditions
present at the time of going off-hook. This resistor
calibration can be disabled by setting the RCALD bit
(Register 25, bit 5).
After the resistor calibration is performed, an ADC
calibration is performed for 256 ms. This calibration
helps to remove offset in the A/D sampling the
telephone line. This ADC calibration can be disabled by
setting the CALD bit (Register 17, bit 5). See
“5.29.Calibration” on page 39. for more information on
automatic and manual calibration.
Silicon Laboratories recommends that the resistor and
the ADC calibrations not be disabled except when a fast
response is needed after going off-hook, such as when
responding to a Type II caller-ID signal. See “5.21.Caller
To calculate the total time required to go off-hook and
start transmission or reception, the digital filter delay
(typically 1.5 ms with the FIR filter) should be included
in the calculation.
5.10. Interrupts
The AOUT/INT pin can be used as a hardware interrupt
pin by setting the INTE bit (Register 2, bit 7). When this
bit is set, the call progress output function (AOUT) is not
available. The default state of this interrupt output pin is
active low, but active high operation can be enabled by
setting the INTP bit (Register 2, bit 6). This pin is an
open-drain output when the INTE bit is set, and requires
a 4.7 k
pullup or pulldown for correct operation. If
multiple INT pins are connected to a single input, the
combined pullup or pulldown resistance should equal
4.7 k
. Bits 7–2, and 0 in Register 3 and bit 1 in
Register 44 can be set to enable hardware interrupt
sources. When one or more of these bits are set, the
AOUT/INT pin becomes active and stays active until the
interrupts are serviced. If more than one hardware
interrupt is enabled in Register 3, software polling
determines the cause of the interrupts. Register 4 and
bit 3 of Register 44 contain sticky interrupt flag bits.
Clear these bits after being set to service the interrupt.
Registers 43 and 44 contain the line current/voltage
threshold interrupt. This interrupt will trigger when either
the measured line voltage or current in the LVS or LCS2
registers, as selected by the CVS bit (Register 44, bit 2),
crosses the threshold programmed into the CVT[7:0]
bits. An interrupt can be programmed to occur when the
measured value rises above or falls below the
threshold. Only the magnitude of the measured value is
used to compare to the threshold programmed into the
CVT[7:0] bits, and thus only positive numbers should be
used as a threshold. This line current/voltage threshold
interrupt is only available with the Si3019 line-side
device.
5.11. DC Termination
The DAA has programmable settings for dc impedance,
minimum operational loop current, and TIP/RING
voltage. The dc impedance of the DAA is normally
represented with a 50
slope as shown in Figure 20,
but can be changed to an 800
slope by setting the
DCR bit. This higher dc termination presents a higher
resistance to the line as loop current increases.
.
Figure 20. FCC Mode I/V Characteristics,
DCV[1:0] = 11, MINI[1:0] = 00, ILIM = 0
For applications that require current limiting per the
TBR21 standard, the ILIM bit can be set to select this
mode. In the current limiting mode, the dc I/V curve is
changed to a 2000
slope above 40 mA, as shown in
Figure 21. The DAA operates with a 50 V, 230
feed,
which is the maximum line feed specified in the TBR21
standard.
12
11
10
9
8
7
6
.01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11
Loop Current (A)
FCC DCT Mode
Voltage
Ac
ro
ss
DAA
(
V
)
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