參數(shù)資料
型號(hào)： SI3015-BS
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 27/64頁(yè)
文件大小： 0K
描述： IC ISOMODEM LINE-SIDE DAA 16SOIC
標(biāo)準(zhǔn)包裝： 48
系列： ISOmodem®
數(shù)據(jù)格式： V.90
波特率： 2.4k
電源電壓： 3.3V，5V
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 管件
Si3038
Rev. 2.01
33
the incoming SDATA_OUT tag bits at the beginning of
each audio output frame to determine which SLOTREQ
bits (bit 4 or 9 in SDATA_IN Slot 1) to set active (low).
SLOTREQ bits asserted during the current audio input
frame signal which active output slots require data from
the AC’97 Digital Controller in the next audio output
frame. An active output slot is defined as any slot
supported by the codec that is not in a power-down
state.
The SLOTREQ signal is dependent on the current
power state. The following is a list of conditions in which
the SLOTREQ for slot 5 is active and conditions in
which it is inhibited:
SLOTREQ is active every frame when the PRD/PRF
is set (Reg 3E, bit 11/13). (DAC is powered down.)
This is required by the AC’97 specification for
compatibility with 48 kHz AC’97 rev. 1.03 codecs.
SLOTREQ is inhibited (high) if the MLNK bit is set
(register 56, bit 12), and AC-Link halt is impending.
Slot 1: Command Address Port
The Command Address Port controls features and
monitors status (see Audio Input Frame Slots 1 and 2)
for Si3038 chipset functions including, but not limited to,
sample
rate,
AFE
configuration,
and
power
management.
The control interface architecture supports up to 64
16-bit read/write registers addressable on even byte
boundaries. Only the even registers (00h, 02h, etc.) are
valid; odd register (01h, 03h, etc.) writes are ignored
and reads return 0. Note that shadowing of the control
register file on the AC’97 controller is an option left open
to the implementation of the AC’97 controller. The
Si3038’s control register file is readable as well as
writable to provide more robust testability.
Audio output frame slot 1 communicates control register
address and write/read command information to the
Si3038 chipset.
Command Address Port bit assignments:
Bit(19)—Read/Write command (1=read, 0=write)
Bit(18:12)—Control Register Index (64 16-bit
locations, addressed on even byte boundaries)
Bit(11:0)—Reserved (padded with 0s)
The first bit (MSB) sampled by the Si3024 indicates
whether the current control transaction is a read or a
write operation. The following seven bit positions
communicate the targeted control register address. The
trailing 12 bit positions within the slot are reserved and
must be padded with 0s by the AC’97 controller.
Slot 2: Command Data Port
The Command Data Port delivers 16-bit control register
write data in the event that the current command port
operation is a write cycle as indicated by Slot 1, bit 19.
Command Data Port bit assignments:
Bit(19:4)—Control Register Write Data (padded with
0s if the current operation is a read)
Bit(3:0)—Reserved (padded with 0s)
Slot 5: Modem Line 1 DAC
Audio output frame slot 5 contains MSB-justified
modem DAC output data for phone line #1 (ID = 0 or 1).
The modem DAC output resolution is 16 bits.
The Si3038 receives its DAC data MSB first.
Slot 5 data is sent by the controller at a rate below the
48 kHz rate of the AC-Link. Therefore, “tags” are used
to mark when there is valid data in slot 5. The tag for
slot 5 is bit 10 in slot 0. Tag bits are sent by the
controller in response to a SLOTREQ on SDATA_IN.
Slot 10: Modem Line 2 DAC
Line 2 is assigned to slot 10. The leading 16-bits of each
slot must contain valid sample data (MSB bit 19,
LSB 4).
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