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參數(shù)資料
| 型號： | SI3012-KT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT |
| 中文描述： | 3.3伏催化裂化/ JATE直接訪問安排 |
| 文件頁數(shù)： | 36/64頁 |
| 文件大小： | 1740K |
| 代理商： | SI3012-KT |
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Si3038
Codec Register Access
36
Rev. 2.01
Whenever the AC’97 Digital Controller addresses the
Si3024 as a primary codec or the codec responds to a
read command, Slot 0 Tag bits should always be set to
indicate actual valid data in Slot 1 and Slot 2. See
Table 23.
When the AC’97 Digital Controller addresses the
Si3024 as a secondary codec, the Slot 0 Tag bits for
Address and Data must be zero. A non-zero, 2-bit
codec ID in the LSBs of Slot 0 indicates a valid Read or
Write Address in Slot 1, and the Slot 1 R/W bit indicates
presence or absence of valid Data in Slot 2. See
Table 24.
In order for the AC’97 Digital Controller to independently
access Primary and Secondary Codec registers, a 2-bit
Codec ID field (chip select) is used in the LSBs of
Output Slot 0.
For Secondary Codec access, the AC’97 Digital
Controller must invalidate the tag bits for Slot 1 and 2
Command Address and Data (Slot 0, bits 14 and 13)
and place a non-zero value (01 or 10) into the Codec ID
field (Slot 0, bits 1 and 0).
When configured as a secondary codec, the Si3024
disregards the Command Address and Command Data
(Slot 0, bits 14 and 13) tag bits when a 2-bit Codec ID
value (Slot 0, bits 1 and 0) is sent that matches the ID
configuration. In a sense, the Secondary Codec ID field
functions as an alternative Valid Command Address (for
Secondary reads and writes) and Command Data (for
Secondary writes) tag indicator.
The Si3024 monitors the Frame Valid bit and ignores
the frame (regardless of the state of the Secondary
Codec ID bits) if it is not valid. The AC’97 Digital
Controllers should set the frame valid bit for a frame
with a secondary register access, even if no other bits in
the output tag slot except the Secondary Codec ID bits
are set. See Table 25.
Table 23. Primary Codec Addressing: Slot 0 Tag Bits
Function
Slot 0, bit 15
(Valid Frame)
Slot 0, bit 14
(Valid Slot 1
Address)
Slot 0, bit 13
(Valid Slot 2
Data)
Slot 0, Bits 1–0
(Codec ID)
AC’97 Digital Controller
Primary Read Frame N, SDATA_OUT
1
1
0
00
AC’97 Digital Controller
Primary Write Frame N, SDATA_OUT
1
1
1
00
Si3024 Status Frame N + 1, SDATA_IN
1
1
1
00
Table 24. Secondary Codec Addressing: Slot 0 Tag Bits
Function
Slot 0, bit 15
(Valid Frame)
Slot 0, bit 14
(Valid Slot 1
Address)
Slot 0, bit 13
(Valid Slot 2
Data)
Slot 0, Bits 1–0
(Codec ID)
AC’97 Digital Controller
Secondary Read Frame N,
SDATA_OUT
1
0
0
01 or 10
AC’97 Digital Controller
Secondary Write Frame N,
SDATA_OUT
1
0
0
01 or 10
Si3024 Status Frame N + 1,
SDATA_IN
1
1
1
00
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