參數(shù)資料
型號(hào)： SI3012-KT
廠商： Electronic Theatre Controls, Inc.
英文描述： 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT
中文描述： 3.3伏催化裂化/ JATE直接訪問(wèn)安排
文件頁(yè)數(shù)： 11/64頁(yè)
文件大?。?/td> 1740K
代理商： SI3012-KT
Si3038
Rev. 2.01
11
Figure 7. AC-Link Low Power Mode Timing Diagram
Figure 8. ATE Test Mode Timing Diagram
Table 12. AC Link Timing Characteristics— Low Power Mode Timing
(V
D
= 3.0 to 3.6 V, V
A
= Charge Pump, T
A
= 25°C, C
L
= 50 pF)
Parameter
Symbol
Min
Typ
Max
Unit
End of Slot 2 to BIT_CLK, SDATA_IN
Low
T
s2_pdown
—
—
1.0
μs
Table 13. ATE Test Mode
(V
D
= 3.0 to 3.6 V, V
A
= Charge Pump, T
A
= 25°C, C
L
= 50 pF)
Parameter
1,2
Symbol
Min
Typ
Max
Unit
Setup to rising edge of RESET (also
applies to SYNC)
T
setup2rst
15.0
—
—
ns
Rising edge of RESET to Hi-Z delay
T
off
—
—
25.0
ns
Notes:
1.
All AC link signals are normally low through the trailing edge of RESET. Bringing SDATA_OUT high for the trailing edge
of RESET causes AC’97 AC-link outputs to go high impedance, which is suitable for ATE in circuit testing.
2.
When the test mode has been entered, AC’97 must be issued another RESET with all AC-link signals low to return to
the normal operating mode.
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
Slot 1
Slot 2
Write to
0x56
Data
MLNK
Don't care
T
s2_pdown
Note: BIT_CLK not to scale
RESET
SDATA_OUT
SDATA_IN, BIT_CLK
T
setup2rst
Hi-Z
T
off
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PDF描述
SI3035 3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT
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