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參數(shù)資料
| 型號(hào)： | sda 9254-2 |
| 廠商： | SIEMENS AG |
| 英文描述： | 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter(應(yīng)用于TV的2.6 M位動(dòng)態(tài)存儲(chǔ)器) |
| 中文描述： | 2.6兆比特的動(dòng)態(tài)影視順序訪問應(yīng)用程序的內(nèi)存（電視，SAM）的具有片上降噪過濾器（應(yīng)用于電視的260萬位動(dòng)態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 182K |
| 代理商： | SDA 9254-2 |
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SDA 9254-2
Semiconductor Group
17
1998-01-16
AC Characteristics
V
DD
= 5 V
±
10 %;
T
A
= 0 to 70
°
C
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
Memory read or
write cycle time
t
RC
240
100000 ns
Operation with
t
RC
≥
t
RCmin
ensures that 8-bit serial
data are shifted out within
one RE cycle taking
t
SC
=
t
SCmin
.
See diagram 2, 3, 4, 6
RE low time
t
RE
t
SC
100
100000 ns
See diagram 2, 3, 4, 6
Serial port cycle
time
30
100000 ns
See diagram 2 – 6
RE precharge time
t
RP
t
AS
t
AH
t
ROS
100
ns
See diagram 2, 3, 4, 6
Address setup time
5
ns
See diagram 2, 3, 4, 6
Address hold time
6
ns
See diagram 2, 3, 4, 6
SCAD to RE
set-up time
3
ns
See diagram 2, 3, 4, 6
RE to SCAD
hold time
t
ROH
10
ns
See diagram 2, 3, 4, 6
RE to RA or RB
delay time
t
RRD
90
ns
t
RRD
and
t
RRL
are restrictive
operating parameters only
in memory read transfer
cycles.
See diagram 2, 3
RA or RB to RE
lead time
t
RRL
– 30
ns
See RE to RA or RB delay
time.
See diagram 2, 3
RA to SCA
RB to SCB
set-up time
t
RSS
0
ns
See diagram 2, 3
RA or RB
pulse width
t
RPW
10
ns
See diagram 2, 3
RA to SCA
RB to SCB
hold time
t
RSH
15
ns
See diagram 2, 3
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| SDA9254-2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter |
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