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參數(shù)資料
| 型號(hào)： | SCN68652AC2F40 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Multi-protocol communications controller MPCC |
| 中文描述： | 1 CHANNEL(S), 2M bps, MULTI PROTOCOL CONTROLLER, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 18/28頁 |
| 文件大?。?/td> | 651K |
| 代理商： | SCN68652AC2F40 |
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Philips Semiconductors
Product specification
SCN2652/SCN68652
Multi-protocol communications controller (MPCC)
1995 May 01
18
TIMING DIAGRAMS
(Continued)
CLOCK
t
CLK1
1/f
TxC
TxSO
t
CLK0
TxD
RxC
RxSI
t
CLK0
t
CLK1
t
RxS
t
RxH
SD00066
Figure 11. Timing Diagrams (cont.)
TRANSMIT – START OF MESSAGE
TxC
SYNC/FLAG
1
1ST CHAR
8 TxC
1
MARK
TxSO
TxBE
DBEN
SET TSOM
LOAD 1st CHAR
RESET TSOM
LOAD 2nd CHAR
TxE
TxA
2
3
NOTES:
1.
SYNC may be 5 to 8 bits and will contain parity bit as specified.
2.
TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been raised.
3.
TxBE goes low relative to DBEN falling edge on the first write transfer into TDSR. It is reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then goes
low relative to DBEN falling edge when writing into TDSR
and/or TDSR
. It is reasserted on the rising edge of the TxC that corresponds to the transmission of the last bit of each
character, except in BOP mode when the CRC is to be sent as the next character (see Transmit Timing–End of Message).
SD00067
Figure 12. Timing Diagrams (cont.)
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