參數(shù)資料
型號(hào): SCF5250PV120
廠商: Motorola, Inc.
英文描述: SCF5250 Integrated ColdFire Microprocessor
中文描述: SCF5250提供了集成的ColdFire微處理器
文件頁(yè)數(shù): 33/48頁(yè)
文件大小: 767K
代理商: SCF5250PV120
Electrical Characteristics
SCF5250 Integrated ColdFire Microprocessor Data Sheet, Rev. 1.1
Freescale Semiconductor
33
Figure 8. I2C Timing Definition
Table 27. I2C Output Bus Timings
Num
Characteristic
96 MHz
Units
Min
Max
M10
3
SCL, SDA Valid to BCLK (input setup)
2
nSec
M11
BCLK to SCL, SDA Invalid (input hold)
4.5
nSec
M12
1
BCLK to SCL, SDA Low (output valid)
10
nSec
M13
2
BCLK to SCL, SDA Invalid (output hold)
3
nSec
1.
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this
specification applies only when SCL or SDA are driven low by the processor. The time required for SCL or
SDA to reach a high level depends on external signal capacitance and pull-up resistor values.
2.
Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this
specification applies only when SCL or SDA are actively being driven or held low by the processor.
3.
SCL and SDA are internally synchronized.This setup time must be met only if recognition on a particular
clock is required.
M2
M6
M1
M4
M7
M8
M9
M5
M3
SCL
SDA
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