參數(shù)資料
型號(hào): SCF5250PV120
廠商: Motorola, Inc.
英文描述: SCF5250 Integrated ColdFire Microprocessor
中文描述: SCF5250提供了集成的ColdFire微處理器
文件頁(yè)數(shù): 29/48頁(yè)
文件大?。?/td> 767K
代理商: SCF5250PV120
Electrical Characteristics
SCF5250 Integrated ColdFire Microprocessor Data Sheet, Rev. 1.1
Freescale Semiconductor
29
Figure 5. Debug Timing Definition
Table 22. Debug AC Timing Specification
Num
Characteristic
Units
Min
Max
D1
PSTCLK to signal Valid (Output valid)
---
6
nSec
D2
PSTCLK to signal Invalid (Output hold)
1.8
nSec
D3
1
Signal Valid to PSTCLK (Input setup)
3
nSec
D4
PSTCLK to signal Invalid (Input hold)
5
nSec
1.
DSCLK and DSI are internally synchronized. This setup time must be met only if recognition
on a particular clock is required.
2.
AC timing specs assume 50pF load capacitance on PSTCLK and output pins. If this value is
different, the input and output timing specifications would need to be adjusted to match the
clock load.
PSTCLK
DSCLK
DSI
PST[3:0]
DDATA[3:0]
DSO
D3
D1
D2
D3
D4
D4
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