參數(shù)資料
型號: SCF5250CPV120
廠商: Motorola, Inc.
英文描述: SCF5250 Integrated ColdFire Microprocessor
中文描述: SCF5250提供了集成的ColdFire微處理器
文件頁數(shù): 9/48頁
文件大?。?/td> 767K
代理商: SCF5250CPV120
Signal Descriptions
SCF5250 Integrated ColdFire Microprocessor Data Sheet, Rev. 1.1
Freescale Semiconductor
9
.
4
Signal Descriptions
4.1
Introduction
This section describes the SCF5250 input and output signals. The signal descriptions as shown in Table
2-A are grouped according to relevant functionality.
Table 2. SCF5250 Documentation
Document Name
Description
Order Number
CFPRM/D
ColdFire Family Programmer’s Reference Manual
CFPRM/D
ColdFire2UM
Version 2/2M ColdFire Core
Processor User’s Manual
ColdFire2UM/D
ColdFire2UMAD
Version 2/2M ColdFire Core
Processor User’s Manual Addendum
ColdFire2UMAD/D
SCF5250UM
SCF5250 User’s Manual
SCF5250UM/D
Table 3. SCF5250 Signal Index
Signal Name
Mnemonic
Function
Input/
Output
Reset
State
Address
A[24:1]
A[23]/GPO54
24 address lines, address line 23
multiplexed with GPO54 and address
24 is multiplexed with A20 (SDRAM
access only).
Out
X
Read-write control
R/W
Bus write enable - indicates if read or
write cycle in progress
Out
H
Output enable
OE
Output enable for asynchronous
memories connected to chip selects
Out
negated
Data
D[31:16]
Data bus used to transfer word data
In/Out
Hi-Z
Synchronous row address
strobe
SDRAS/GPIO59
Row address strobe for external
SDRAM.
Out
negated
Synchronous column
address strobe
SDCAS/GPIO39
Column address strobe for external
SDRAM
Out
negated
SDRAM write enable
SDWE/GPIO38
Write enable for external SDRAM
Out
negated
SDRAM upper byte enableSDUDQM/GPO53
Indicates during write cycle if high byte
is written
Out
SDRAM lower byte enable SDLDQM/GPO52
Indicates during write cycle if low byte
is written
Out
SDRAM chip selects
SD_CS0/GPIO60
SDRAM chip select
In/Out
negated
SDRAM clock enable
BCLKE/GPIO63
SDRAM clock enable
Out
System clock
BCLK/GPIO40
SDRAM clock output
In/Out
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