參數(shù)資料
型號(hào)： SCF5250CPV120
廠商： Motorola, Inc.
英文描述： SCF5250 Integrated ColdFire Microprocessor
中文描述： SCF5250提供了集成的ColdFire微處理器
文件頁(yè)數(shù)： 6/48頁(yè)
文件大?。?/td> 767K
代理商： SCF5250CPV120
SCF5250 Integrated ColdFire Microprocessor Data Sheet, Rev. 1.1
Introduction
1.2.18 I
2
C Module
The two-wire I
2
C bus interface, which is compliant with the Philips I
2
C bus standard, is a bidirectional
serial bus that exchanges data between devices. The I
2
C bus minimizes the interconnection between
devices in the end system and is best suited for applications that need occasional bursts of rapid
communication over short distances among several devices. Bus capacitance and the number of unique
addresses limit the maximum communication length and the number of devices that can be connected.
Freescale Semiconductor
6
1.2.19 Chip-Selects
Up to four programmable chip-select outputs provide signals that enable glueless connection to external
memory and peripheral circuits. The base address, access permissions and automatic wait-state insertion
are programmable with configuration registers. These signals also interface to 16-bit ports.
CS0 is active after reset to provide boot-up from external FLASH/ROM.
1.2.20 GPIO Interface
A total of 60 General Purpose inputs and 57 General Purpose outputs are available. These are multiplexed
with various other signals. Seven of the GPIO inputs have edge sensitive interrupt capability.
1.2.21 Interrupt Controller
The interrupt controller provides user-programmable control of a total of 57 interrupts. There are 49
internal interrupt sources. In addition, there are 7 GPIOs where interrupts can be generated on the rising
or falling edge of the pin. All interrupts are autovectored and interrupt levels are programmable.
1.2.22 JTAG
To help with system diagnostics and manufacturing testing, the SCF5250 includes dedicated
user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability,
often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1A
standard. Freescale provides BSDL files for JTAG testing.
1.2.23 System Debug Interface
The ColdFire processor core debug interface supports real-time instruction trace and debug, plus
background-debug mode. A background-debug mode (BDM) interface provides system debug.
In real-time instruction trace, four status lines provide information on processor activity in real time (PST
pins). A four-bit wide debug data bus (DDATA) displays operand data and change-of-flow addresses,
which helps track the machine’s dynamic execution path.
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