參數(shù)資料
型號(hào)： SCANPSC110FLMQB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28
封裝： LCC-28
文件頁(yè)數(shù)： 25/29頁(yè)
文件大小： 459K
代理商： SCANPSC110FLMQB
Applications Example
(Continued)
More Information can be found in Application Notes:
AN-1023
Structural System Test via IEEE Std. 1149.1 with
SCANPSC110F Hierarchical and Multidrop Ad-
dressable JTAG Port
AN-1022
Boundary Scan, An Enabling Technology for
System Level Embedded Test
1.
After the system is powered up a level-1 reset is per-
formed via the TRST input. All TAP Controllers (both
’PSC110F and local) are asynchronously forced into the
Test-Logic-Reset state. All LSP Controllers are in the
parked Test-Logic-Resetstate; this forces the TMS
out-
puts of each port to a logic “1”, keeping all board TAPs in
the Test-Logic-Reset state.
2.
The first task of the tester is to find out which slots are
occupied on the backplane. This is accomplished by per-
forming a serial poll of each slot address in the system,
as assigned by the S
0–5
value of each ’PSC110F in the
system.
Each target slot address is addressed by first sequenc-
ing all ’PSC110Fs on the backplane to the Shift-IRstate,
and then by shifting in the address of the target slot. The
’PSC110F TAP controller is then sequenced through the
Update-IR state. If a ’PSC110F with the matching slot
identification is present, it is selected. All other
’PSC110Fs are unselected. To determine whether that
slot contains a selected ’PSC110F, the tester must read
back the ’PSC110Fs S
0–5
value (if present).
The tester moves the selected ’PSC110F from the
Update-IR state back to the Shift-IR state, and the in-
struction register is then scanned while loading the next
instruction (GOTOWAIT) During the Capture-IR state of
the TAP Controller, a “01” pattern is loaded into the two
least significant bits of the ’PSC110F’s instruction regis-
ter, and the most significant six bits capture the value on
the S
pins. The captured data is shifted out while the
GOTOWAIT command is shifted in. If an “all ones” pat-
tern is returned, a board does not exist at that location.
(The “all ones” pattern is caused by the pull-up resistor
on the TDI input of the controller, as required for 1149.1
compliance.)
At the end of instruction register scan, the GOTOWAIT
command is issued and all ’PSC110F selection control-
lers enter the Wait-For-Address state. This allows the
next ’PSC110F in the polling sequence to be addressed.
The polling process is repeated for every possible board
address in the system. In this example, the tester finds
that boards
#
1 through
#
8 are present, and boards
#
9
and
#
10 are missing. Therefore, it will report back its
findings and will not attempt to test the missing boards.
3.
Infrastructure testing of the populated boards may now
proceed. The tester addresses the ’PSC110F on Board
#
1 for test operations. ’PSC110F
#
1 is now selected,
while all others are unselected.
Board
#
1 is wired such that all LSP
’s are connected to
individual scan chains. The first objective is to test the
scan chain integrity of the board. For this task, it is more
efficient to configure the LSPN such that all three chains
are placed in series. To accomplish this, the MODESEL
instruction is issued to place the mode register into the
active scan chain, and the binary value “00000111” is
shifted into the mode register. The UNPARK instruction
is then issued to access all three local chains.
Once the UNPARK instruction has been updated and
the ’PSC110F TAP controller is synchronized with the lo-
cal TAP’s, the scan chain integrity test can be performed
on the local scan chains. This test is done by performing
a Capture-IR and then shifting the scan chain checking
the 2 least significant bits of each components instruc-
tion register for “01”. If the LSB’s of any component in
the scan chain are not “01”, the test fails. Diagnostic
software can be used to narrow down the cause of the
failure. Next the device identification of each component
in the scan chain is checked. This is done by issuing the
IDCODE instruction to each component in the scan
chain. Components that do not support IDCODE will in-
sert their bypass register into the active scan chain.
After the IDCODE register scan, the GOTOWAIT in-
struction is issued to reset the local scan ports and re-
turn
the
’PSC110F
Selection
Wait-For-Address state. A sequence similar to step 3 is
repeated for each board in the system.
Next, the tester addresses Board
#
1 to perform intercon-
nect testing. For this task, it is efficient to configure the
LSPN such that all three chains are placed in series.
Therefore, the Mode register should be programmed
with the binary value “00000111” (this was done in step
3
above
and
need
not
Test-Logic-Reset was performed since then). The UN-
PARK instruction is issued to access all three local
chains.
Once the UNPARK instruction has been loaded and the
’PSC110F is synchronized with the local TAPs, normal
1149.1 scan operations may commence. To test the in-
terconnect on Board
#
1, an instruction register scan se-
quence is performed and the SAMPLE/PRELOAD in-
struction is loaded into the instruction register of all
target devices. The BYPASS instruction is loaded into
the instruction register of ’PSC110F
#
1. A data register
scan is now performed to preload the first test vector to
be applied to the interconnect.
After the preload operation is performed, an instruction
register scan is used to load the EXTESTinstruction into
all TAPs (BYPASS loaded into ’PSC110F
#
1). The ap-
propriate sequencing is now performed to apply patterns
in order to test the interconnect on Board
#
1.
Upon completion of the interconnect test on Board
#
1,
the local chains must be parked. The PARKTLR com-
mand is loaded into the instruction register, and the
TMS
outputs of the three local chains are forced high,
sending the three local TAPs into the Test-Logic-Reset
state.
Now that the Board
#
1 interconnect has been tested, the
interconnect on the other boards in the system must be
checked.
All
’PSC110F
Wait-For-Address state by issuing the GOTOWAlT in-
struction. Board
#
2 is addressed next, followed by the
rest of the boards in the system. A sequence similar to
steps 4 through 6 is used for each board.
controller
to
the
4.
be
repeated
unless
a
5.
6.
7.
are
returned
to
the
S
www.national.com
25
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