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參數(shù)資料
| 型號： | SCANPSC110FFMQB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDFP28 |
| 封裝： | FP-28 |
| 文件頁數(shù)： | 8/29頁 |
| 文件大?。?/td> | 459K |
| 代理商： | SCANPSC110FFMQB |
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Overview of SCANPSC110F Bridge
Functions
(Continued)
Following
state-machine is in the Test-Logic-Reset (TLR) state; the
’PSC110F-selection
state-machine
Wait-For-Address state; and each of the three port-selection
state-machines is in the Parked-TLR state. The ’PSC110F is
then ready to receive Level-1 protocol, followed by Level-2
protocol.
a
hardware
reset,
the
TAP
controller
is
in
the
Tester/SCANPSC110F Bridge
Interface
An IEEE 1149.1 system tester sends instructions to a
’PSC110F via that ’PSC110F’s backplane scan-port. Follow-
ing test logic reset, the ’PSC110F’s selection state-machine
is in the Wait-For-Address state. When the ’PSC110F’s TAP
controller is sequenced to the Shift-IR state, data shifted in
through the TDI
input is shifted into the ’PSC110F’s instruc-
tion register. Note that prior to successful selection of a
’PSC110F, data is not shifted out of the instruction register
and out through the ’PSC110F’s TDO
output, as it is during
normal scan operations. Instead, as each new bit enters the
instruction register’s most-significant bit, data shifted out
from the least-significant bit is discarded.
Register Set
The SCANPSC110F Bridge includes a number of registers
which are used for ’PSC110F selection and configuration,
scan data manipulation, and scan-support operations. These
registers can be grouped as shown in Table 3
The specific fields and functions of each of these registers
are detailed in the section of this document titled “Data Reg-
ister Descriptions”.
When the instruction register is updated with the address
data, the ’PSC110F’s address-recognition logic compares
the six least-significant bits of the instruction register with the
6-bit assigned address which is statically present on the
S
inputs. Simultaneously, the scanned-in address is
compared with the reserved Broadcast and Multi-cast ad-
dresses.
If
an
address
’PSC110F-selection state-machine enters one of the two se-
lected states. If the scanned address does not match a valid
single-slot address or one of the reserved broadcast/
multi-cast addresses, the ’PSC110F-selection state-machine
enters the Unselected state.
Note that the SLOT inputs should not be set to a value cor-
responding to a multi-cast group or to the broadcast ad-
dress Also note that the single-’PSC110F selection process
must be performed for all ’PSC110Fs which are subse-
quently to be addressed in multi-cast mode. This is required
because each such device’s Multi-cast Group Register
(MCGR) must be programmed with a multi-cast group num-
ber, and the MCGR is not accessible to the test controller un-
til
that
’PSC110F
has
Selected-Single-’PSC110F state.
Once a ’PSC110F has been selected, Level-2 protocol is
used to issue commands and to access the chip’s various
registers.
match
is
detected,
the
first
entered
the
Note that when any of these registers is selected for inser-
tion into the ’PSC110F’s scan-chain, scan data enters
through that register’s most-significant bit. Similarly, data
that is shifted out of the register is fed to the scan input of the
next-downstream device in the scan-chain.
TABLE 3. Registers
Register Name
BSDL Name
INSTRUCTION
Description
Instruction Register
’PSC110F addressing and instruction-decode
IEEE Std. 1149.1 required register
IEEE Std. 1149.1 required register
IEEE Std. 1149.1 required register
IEEE Std. 1149.1 optional register
’PSC110F-group address assignment
’PSC110F local-port configuration and control bits
’PSC110F scan-data compaction (signature generation)
Local-port TCK clock-gating (for BIST)
Boundary-Scan Register
Bypass Register
Device Identification Register
Multi-Cast Group Register
Mode Register
Linear-Feedback Shift Register
TCK Counter Register
BOUNDARY
BYPASS
IDCODE
MCGR
MODE
LFSR
CNTR
Addressing Scheme
The SCANPSC110F Bridge architecture extends the func-
tionality of the IEEE 1149.1 Standard by supplementing that
protocol with an addressing scheme which allows a test con-
troller to communicate with specific ’PSC110Fs within a net-
work of ’PSC110Fs. That network can include both
multi-drop and hierarchical connectivity. In effect, the
’PSC110F architecture allows a test controller to dynamically
select specific portions of such a network for participation in
scan operations. This allows a complex system to be parti-
tioned into smaller blocks for testing purposes.
The ’PSC110F provides two levels of test-network partition-
ing capability. First, a test controller can select entire indi-
vidual ’PSC110Fs, specific sets of ’PSC110Fs (multi-cast
groups),
or
all
’PSC110Fs
’PSC110F-selection process is supported by a “Level-1”
communication protocol. Second, within each selected
’PSC110F, a test controller can select one or more of the
chip’s three local scan-ports. That is, individual local ports
can be selected for inclusion in the (single) scan-chain which
a ’PSC110F presents to the test controller. This mechanism
allows a controller to select specific terminal scan-chains
within the overall scan network. The port-selection process is
supported by a “Level-2” protocol.
(broadcast).
This
S
www.national.com
8
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| SCANPSC110FLMQB | 功能描述:IC BRIDGE LCC SCAN MUL JTAG PORT RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:* 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| SCANPSC110FSC | 功能描述:特定功能邏輯 SCAN JTAG Port RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SCANPSC110FSCX | 功能描述:特定功能邏輯 SCAN JTAG Port RoHS:否 制造商:Texas Instruments 產(chǎn)品: 系列:SN74ABTH18502A 工作電源電壓:5 V 封裝 / 箱體:LQFP-64 封裝:Tube |
| SCANSTA101 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
| SCANSTA101_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Voltage IEEE 1149.1 STA Master |
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