參數(shù)資料
型號： SCANPSC110FFMQB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support)
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, CDFP28
封裝： FP-28
文件頁數(shù)： 15/29頁
文件大?。?/td> 459K
代理商： SCANPSC110FFMQB
Register Descriptions
(Continued)
TABLE 7. Mode Register Control of LSPN
Mode Register
Scan Chain Configuration (If unparked)
TDI
B
→
Register
→
TDO
B
TDI
B
→
Register
→
LSP
1
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
2
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
1
→
PAD
→
LSP
2
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
3
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
1
→
PAD
→
LSP
3
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
2
→
PAD
→
LSP
3
→
PAD
→
TDO
B
TDI
B
→
Register
→
LSP
1
→
PAD
→
LSP
2
→
PAD
→
LSP
3
→
PAD
→
TDO
B
TDI
B
→
Register
→
TDO
B
(Loopback)
XXX0X000
XXX0X001
XXX0X010
XXX0X011
XXX0X100
XXX0X101
XXX0X110
XXX0X111
XXX1XXXX
X = don’t care
Register = ’PSC110F instruction register or any of the ’PSC110F test data registers
PAD = insertion of a 1-bit register for synchronization
Mode Register
The mode register is an 8-bit data register used primarily to
configure the Local Scan Port Network. The mode register is
initialized
to
“00000001”
Test-Logic-Reset state.
Bits 0, 1, 2, and 4 are used for scan chain configuration as
described in Table 7 When the UNPARK instruction is ex-
ecuted, the scan chain configuration will be as shown in
Table 7 above. When all LSPs are parked, the scan chain
configuration will be TDI
→
’PSC110F-register
→
TDO
B
. Bit 3
is used for TCK
Ln
configuration, see Table 8
binary
upon
entering
the
TABLE 8. Test Clock Configuration
Bit 3
1
0
1
0
LSP
n
TCK
Ln
Parked
Parked
Unparked
Unparked
Stop
Run
Run
Run
Bit 3 is normally set to logic “0” so that TCK
is free-running
when the local scan ports are parked. When the local ports
are parked, bit 3 can be programmed with logic “1”, forcing
all of the LSP TCK
’s to stop. This feature can be used in
power sensitive applications to reduce the power consumed
by the test circuitry in parts of the system that are not under
test.
Bit 3 of the mode register must be reset to logic “0”
before the UNPARK instruction is executed.
Bit 7 is a status bit for the TCK counter. When the counter is
on and has reached terminal count (Zero) Bit 7 of the mode
register will be high (logic “1”). Bit 7 is read-only and will be
low in all other conditions.
Bits 5 and 6 are reserved for future use.
Device Identification Register
The device identification register (IDREG) is a 32-bit register
compliant with IEEE Std. 1149.1. When the IDCODEinstruc-
tion is active, the identification register is loaded with the
value “0FC0E01F” Hex upon leaving the Capture-DR state
(on the rising edge of the TCK
B
).
TABLE 9. Detailed Device Identification (Binary)
Bits
31–28
Version
Bits 27–12
Bits 11–1
Bit
0
1
Part Number
Manufacturer
Identity
0000 0001 111
0000
1111 1100 0000
1110
1
Linear Feedback Shift Register
The ’PSC110F contains a “signature compactor” which sup-
ports test result evaluation in a multi-chain environment. The
signature compactor consists of a 16-bit linear-feedback shift
register (LFSR) which can monitor local-port scan data as it
is shifted “upstream” from the ’PSC110F’s local-port net-
work. Once the LFSR is enabled, the LFSR’s state changes
in a reproducible way as each local-port data bit is shifted in
from the local-port network. When all local-port data has
been scanned in, the LFSR contains a 16-bit signature value
which can be compared against a signature computed for
the expected results vector.
The LFSR uses the following feedback polynomial:
F(x) = X
16
+ X
12
+ X
3
+ X + 1
This signature compactor is used to compress serial data
shifted in from the local scan chain, into a 16-bit signature.
This signature can then be shifted out for comparison with an
expected value. This allows users to test long scan chains in
parallel, via Broadcast or Multi-Cast addressing modes, and
check only the 16-bit signatures from each module.
The LFSR is initialized with a value of “0000” Hex upon re-
set.
32-Bit TCK Counter Register:
The 32-bit TCK counter register enables BIST testing that re-
quires “n” TCK cycles, to be run on a parked LSP while an-
other ’PSC110F port is being tested. The CNTRSEL instruc-
tion can be used to load a count-down value into the counter
register via the active scan chain. When the counter is en-
abled (via the CNTRON instruction), and the LSP is parked,
the local TCKs will stop and be held low when terminal count
is reached.
The TCK counter is initialized with a value of “00000000”
Hex upon reset.
S
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