
AC Electrical Characteristics
(Continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 6)
Symbol
t
PHZ
t
PLZ
t
PZH
t
PZL
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t
PHLD
Differential Prop. Delay High to Low (Note 8)
t
PLHD
Differential Prop Delay Low to High (Note 8)
t
SDK1
Differential Skew |t
PHLD
–t
PLHD
| (Note 9)
t
SDK2
Chip to Chip Skew (Note 12)
t
SDK3
Channel to Channel skew (Note 13)
t
TLH
Transition Time Low to High
t
THL
Transition Time High to Low
t
PHZ
Disable Time High to Z
t
PLZ
Disable Time Low to Z
t
PZH
Enable Time Z to High
t
PZL
Enable Time Z to Low
SCAN CIRCUITRY TIMING REQUIREMENTS
f
MAX
Maximum TCK Clock Frequency
t
S
TDI to TCK, H or L
t
H
TDI to TCK, H or L
t
S
TMS to TCK, H or L
t
H
TMS to TCK, H or L
t
W
TCK Pulse Width, H or L
t
W
TRST Pulse Width, L
t
REC
Recovery Time, TRST to TCK
Parameter
Conditions
R
L
= 27
,
Figure 4
,
Figure 5
C
L
= 10 pF
Min
Typ
3
3
3
3
Max
8
8
8
8
Units
ns
ns
ns
ns
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Figure 6
,
Figure 7
C
L
= 35 pF
2.0
2.0
2.4
2.4
210
3.9
3.9
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
1.9
0.7
2.5
2.5
10
8
8
8
0.35
1.5
1.5
4.5
3.5
3.5
3.5
R
L
= 500
,
Figure 8
,
Figure 9
C
L
= 35 pF
R
L
= 500
, C
L
= 35
pF
25.0
1.5
1.5
2.5
1.5
10.0
2.5
2.0
75.0
MHz
ns
ns
ns
ns
ns
ns
ns
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2:
All currents into device pins are positive; all currents out of device pins are negative.All voltages are referenced to ground unless otherwise specified except
V
OD
,
V
OD
and V
ID
.
Note 3:
All typicals are given for V
CC
= +3.3V and T
A
= +25C, unless otherwise stated.
Note 4:
ESD Rating: HBM (1.5 k
, 100 pF)
>
4.5 kV EIAJ (0
, 200 pF)
>
300V.
Note 5:
C
L
includes probe and fixture capacitance.
Note 6:
Generator waveforms for all tests unless otherwise specified: f = 25 MHz, Z
O
= 50
, t
r
, t
f
=
<
1.0 ns (0%–100%). To ensure fastest propagation delay and
minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate,
the better the AC performance.
Note 7:
The DS92LV090A functions within datasheet specification when a resistive load is applied to the driver outputs.
Note 8:
Propagation delays are guaranteed by design and characterization.
Note 9:
t
SKD1
|t
PHLD
–t
PLHD
| is the worse case skew between any channel and any device over recommended operation conditions.
Note 10:
Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.
Note 11:
V
OH
failsafe terminated test performed with 27
connected between RI+ and RI inputs. No external voltage is applied.
Note 12:
Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
Note 13:
Channel to Channel skew is the difference in driver output or receiver output propagation delay between any channels within a device, common edge.
S
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