參數(shù)資料
型號(hào): SC9318FB
廠商: 杭州士景電子有限公司
英文描述: DIGITAL TUNING SYSTEM
中文描述: 數(shù)字調(diào)諧系統(tǒng)
文件頁(yè)數(shù): 7/36頁(yè)
文件大小: 671K
代理商: SC9318FB
Silan
Semiconductors
SC9318-033
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Rev: 1.0 2002-01-16
7
PIN DESCRIPTION
Pin
No.
Symbol
Pin Name
Internal
Connection
Description
1
COM1
2
COM2
3
COM3
LCD common
output
V
LCD
V
EE
Output common signal to the LCD panel.
Through a matrix with pins S1~S23, a
maximum of 69 segments can be displayed.
Three levels, V
LCD
, V
EE
, and GND, are output
at 83Hz every 2ms. V
EE
is output after
SYSTEM RESET and CLOCK STOP are
released, and a common signal is output after
the DISP OFF bit is set to “0”.
4~18
S1~S15
LCD segment
output
19~26
S16/KR7
~
S23/KR0
LCD segment
output/Key
return timing
output
V
LCD
Segment signal output pins for the LCD panel.
Together with COM1, COM2, and COM3, a
matrix is formed that can display a maximum of
69 segments. The signals for the key matrix
and
the
segment
signals
from
pins
S16/KR7~S23/KR0 are output on a time
division basis. 4 X 8=32 key matrix can be
created in conjunction with key input ports
K0~K3.
27~30
K0~K3
Key input
ports
R
I
R
I
4 bit input ports for key matrix input. Combined
in a matrix with key return timing outputs the
LCD segment pins, data from a maximum of
4X8=32 keys can be input and pins are pulled
up. On the key setting output pin, data from
4X6=24 keys can be input and pins are pulled
down. The WAIT mode is released when high
level is applied to key input ports set to pull-
down.
31~36
T0~T5
Key return
timing output
port
R
O
These ports output the timing signal for key
matrix. To form the key matrix, load resistance
has been built-in the N-channel side. When the
key matrix combined with push-key that does
not need a key matrix diode.
(To be continued)
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