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參數(shù)資料
| 型號： | SC88E43 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | EXTENDED VOLTAGE CALLING NUMBER IDENTIFICATION CIRCUIT 2 |
| 中文描述： | 更廣的電壓主叫號碼識別電路2 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 389K |
| 代理商： | SC88E43 |
Silan
Semiconductors
SC88E43
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Rev: 1.0
2000.12.31
15
Interrupt
To facilitate interfacing with microcontrollers running interrupt driven firmware, an open drain interrupt output
INT
is provided.
INT
is asserted when
TRIGout
is low, StD is high, or
DR
is low. When
INT
is asserted, these
signals should be read (into an input port of the microcontroller) to determine the cause of the interrupt (
TRIGout
,
StD or
DR
) so that the appropriate response can be made.
When system power is first applied,
TRIGout
will be low because capacitor C3 at
TRIGRC
(see Figure 3) has
no initial charge. This will result in an interrupt upon power up. Also when system power is first applied and the
PWDN pin is low, an interrupt will occur due to StD. Since there is no charge across the capacitor at the St/GT pin
in Figure 4, StD will be high triggering an interrupt. The interrupts will not clear until both capacitors are charged.
The microcontroller should ignore interrupt from these msources on initial power up until there is sufficient time to
charge the capacitors.
It is possible to clear StD and its interrupt by asserting PWDN immediately after system power up. When PWDN
is high, StD is low. PWDN will also force both ESt and the comparator output low, Q2 will turn on so that the
capacitor at the St/GT pin charges up quickly (refer to Figure 4).
Power Down Mode
For applications requiring reduced power consumption, the SC88E43 can be powered up only when it is required,
that is, upon detection of one of three CLIP/CID call arrival indicators: line reversal, ring burst and ringing.
The SC88E43 is powered down by setting the PWDN pin to logic high. In power down mode, the oscillator, input
opamp and all internal circuitry are disabled except for TRIGin,
TRIGRC
and
t
TRIGou
pins. These three pins are
not affected by power down, such that, the SC88E43 can still react to call arrival indicators. The SC88E43 can be
powered up by setting the PWDN pin to logic low.
Crystal Oscillator
The SC88E43 requires a 3.579545MHz crystal oscillator as the master timing source.
10
11
OSCI OSCO
SC88E43
3.579545 MHz
10
11
OSCI
OSCO
SC88E43
10
11
OSCI OSCO
SC88E43
to the next
SC88E43
Figure 8 Common Crystal Connection
The crystal specification is as follows :
Frequency:
Frequency tolerance:
C)
Resonance mode:
Load capacitance:
Maximum series resistance: 150 ohms
Maximum drive level (mW): 2 mW
3.579545 MHz
±0.1%(-40 o C+85 o
Parallel
18 pF
Any number of SC88E43 devices can be connected as shown in Figure 8 such that only one crystal is required.
The connection between OSC2 and OSC1 can be DC coupled as shown, or the OSC1 input on all devices can be
driven from a CMOS buffer (dc coupled) with the OSC2 outputs left unconnected.
To meet BT and Bellcore requirements for proper tone detection the crystal must have a frequency tolerance of
0.1%.
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