參數(shù)資料
型號(hào)： SC88E43
廠商： Electronic Theatre Controls, Inc.
英文描述： EXTENDED VOLTAGE CALLING NUMBER IDENTIFICATION CIRCUIT 2
中文描述： 更廣的電壓主叫號(hào)碼識(shí)別電路2
文件頁(yè)數(shù)： 12/25頁(yè)
文件大小： 389K
代理商： SC88E43
Silan
Semiconductors
SC88E43
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Rev: 1.0
2000.12.31
12
BT also specifies that the TE is required to apply a DC wetting pulse and an AC load 15-25ms after the end of the
alerting signal. If t
ABS
=t
DA
+t
GA
is 15 to 25ms, the DC current wetting pulse and the AC load can both be applied
at the falling edge of StD. The maximum t
DA
is 8ms so t
GA
should be 15-17ms. Therefore, t
GP
must be greater
than t
GA
. Figure 5(a) shows a possible implementation. The values in Figures 9 and 11 (R2=R3=422K, C=0.1mF)
will meet the BT timing requirements.
24
23
22
V
DD
St/GT
ESt
C
R1
R2
V
D
=diode forward voltage
SC88E43
(a) t
GP
> t
GA
t
GP
=R1Cln[V
DD
/(V
DD
-V
)]
t
=RpCln[(V
-V
D
(Rp/R2))/(V
TGt
-V
D
(Rp/R2))]
Rp=R1R2/(R1+R2)
24
23
22
V
DD
St/GT
ESt
C
R1
R2
V
D
=diode forward voltage
SC88E43
(b) t
GP
< t
GA
t
GP
=RpCln[(V
DD
-V
D
(Rp/R2))/(V
DD
-V
TGt
-V
D
(Rp/R2))]
t
=R1Cln[V
/V
)]
Rp=R1R2/(R1+R2)
Figure 5 Guard Time Circuits With Unequal Times
Input Configuration
The SC88E43 provides an input arrangement comprised of an operational amplifier, and a bias source (Vref )
which is used to bias the opamp inputs at V
DD
/2. The feedback resistor at the opamp output (GS) can be used to
adjust the gain. In a single-ended configuration, the opamp is connected as shown in Figure 6. For a differential
input configuration, Figure 7 shows the necessary connections.
3
2
1
4
C
R
IN
R
F
IN+
GS
IN-
V
Ref
Voltage Gain
(A
V
) = R
F
/R
IN
Figure 6 Single Ended Input Configuration
3
2
1
4
C
R
4
IN+
GS
IN-
V
Ref
Differental Input Amplifler
C1=C2
R1R4 (For unity gain R5=R4)
R3=(R2R5)/(R2+R5)
Voltage Gain
(AVdiff)=R5/R1 (see Figure 9,10,11)
Input Impedance
(ZINdiff)=2R1
2
+(1/C)
2
C
R
1
R
2
R
3
R
5
Figure 7 Differential Input Configuration
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