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參數(shù)資料
| 型號： | SC80C52XXX-36/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | SIDE BRAZED, 40 PIN |
| 文件頁數(shù)： | 65/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | SC80C52XXX-36/883 |
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44
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor off, PUExn has to be
written logic zero.
Table 10-1 summarizes the control signals for the pin value.
Table 10-1. Port Pin Configurations
Port pins are tri-stated when a reset condition becomes active, even when no clocks are running.
10.2.2 Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI
instruction can be used to toggle one single bit in a port.
10.2.3 Break-Before-Make Switching
In Break-Before-Make mode, switching the DDRxn bit from input to output introduces an immediate tri-state period
lasting one system clock cycle, as indicated in Figure 10-3. For example, if the system clock is 4 MHz and the DDRxn is
written to make an output, an immediate tri-state period of 250 ns is introduced before the value of PORTxn is seen on
the port pin.
To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system clock cycles. The Break-
Before-Make mode applies to the entire port and it is activated by the BBMx bit. For more details, see “PORTCR – Port
When switching the DDRxn bit from output to input no immediate tri-state period is introduced.
DDxn
PORTxn
PUExn
I/O
Pull-up
Comment
0
X
0
Input
No
Tri-state (hi-Z)
0
X
1
Input
Yes
Sources current if pulled low externally
1
0
Output
No
Output low (sink)
1
0
1
Output
Yes
NOT RECOMMENDED.
Output low (sink) and internal pull-up active. Sources
current through the internal pull-up resistor and consumes
power constantly
1
0
Output
No
Output high (source)
1
Output
Yes
Output high (source) and internal pull-up active
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