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參數(shù)資料
| 型號(hào)： | SC80C52XXX-36/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | SIDE BRAZED, 40 PIN |
| 文件頁(yè)數(shù)： | 26/109頁(yè) |
| 文件大?。?/td> | 10824K |
| 代理商： | SC80C52XXX-36/883 |
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271
7593L–AVR–09/12
AT90USB64/128
If the endpoint uses two banks, the second one can be read by the HOST while the current is
being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already
ready (free) and TXINI is set immediately.
23.14.2.1
Abort
An “abort” stage can be produced by the host in some situations:
In a control transaction: ZLP data OUT received during a IN stage
In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN
stage on the IN endpoint
...
The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to per-
form the following operations:
Table 23-1.
Abort flow.
23.15 Isochronous mode
23.15.1
Underflow
An underflow can occur during IN stage if the host attempts to read a bank which is empty. In
this situation, the UNDERFI interrupt is triggered.
An underflow can also occur during OUT stage if the host send a packet while the banks are
already full. Typically, he CPU is not fast enough. The packet is lost.
It is not possible to have underflow error during OUT stage, in the CPU side, since the CPU
should read only if the bank is ready to give data (RXOUTI=1 or RWAL=1)
23.15.2
CRC error
A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI interrupt is triggered. This does not prevent the RXOUTI interrupt
from being triggered.
Endpoint
Abort
Abort done
Abort is based on the fact
that no banks are busy,
meaning that nothing has to
be sent.
Disable the TXINI interrupt.
Endpoint
reset
NBUSYBK
=0
Yes
Clear
UEIENX.
TXINE
No
KILLBK=1
Yes
Kill the last written
bank.
Wait for the end of the
procedure.
No
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| SJ80C32XXX-12SV | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
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