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型號(hào)：	SC80C52XXX-12SV
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
封裝：	0.600 INCH, SIDE BRAZED, DIP-40
文件頁(yè)數(shù)：	272/1021頁(yè)
文件大?。?/td>	15196K
代理商：	SC80C52XXX-12SV

32072H–AVR32–10/2012

AT32UC3A3

Arbitration for HSB Master Interface

Each DMACA channel has two request lines that request ownership of a particular master bus

interface: channel source and channel destination request lines.

Source and destination arbitrate separately for the bus. Once a source/destination state

machine gains ownership of the master bus interface and the master bus interface has owner-

ship of the HSB bus, then HSB transfers can proceed between the peripheral and the DMACA.

An arbitration scheme decides which of the request lines (2 * DMAH_NUM_CHANNELS) is

granted the particular master bus interface. Each channel has a programmable priority. A

request for the master bus interface can be made at any time, but is granted only after the cur-

rent HSB transfer (burst or single) has completed. Therefore, if the master interface is

transferring data for a lower priority channel and a higher priority channel requests service, then

the master interface will complete the current burst for the lower priority channel before switch-

ing to transfer data for the higher priority channel.

If only one request line is active at the highest priority level, then the request with the highest pri-

ority wins ownership of the HSB master bus interface; it is not necessary for the priority levels to

If more than one request is active at the highest requesting priority, then these competing

requests proceed to a second tier of arbitration:

If equal priority requests occur, then the lower-numbered channel is granted.

In other words, if a peripheral request attached to Channel 7 and a peripheral request attached

to Channel 8 have the same priority, then the peripheral attached to Channel 7 is granted first.

Memory Peripherals

Figure 19-3 on page 319 shows the DMA transfer hierarchy of the DMACA for a memory periph-

eral. There is no handshaking interface with the DMACA, and therefore the memory peripheral

can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately

without waiting for a transaction request. The alternative to not having a transaction-level hand-

shaking interface is to allow the DMACA to attempt System Bus transfers to the peripheral once

the channel is enabled. If the peripheral slave cannot accept these System Bus transfers, it

inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait

states be inserted onto the bus. By using the handshaking interface, the peripheral can signal to

the DMACA that it is ready to transmit/receive data, and then the DMACA can access the

peripheral without the peripheral inserting wait states onto the bus.

Handshaking Interface

Handshaking interfaces are used at the transaction level to control the flow of single or burst

transactions. The operation of the handshaking interface is different and depends on whether

the peripheral or the DMACA is the flow controller.

The peripheral uses the handshaking interface to indicate to the DMACA that it is ready to trans-

fer/accept data over the System Bus. A non-memory peripheral can request a DMA transfer

through the DMACA using one of two handshaking interfaces:

Hardware handshaking

Software handshaking

相關(guān)PDF資料	PDF描述
MR80C52CXXX-12/883:D	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
MC80C52EXXX-12SC	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40
MD80C52TXXX-16SHXXX:D	8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
MR80C52CXXX-12SCR	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
MQ80C52XXX-25	8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44

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