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| 型號(hào)： | SC68L198 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
| 中文描述： | 八路與TTL兼容的UART在3.3V和5V電源電壓 |
| 文件頁數(shù)： | 24/49頁 |
| 文件大?。?/td> | 358K |
| 代理商： | SC68L198 |
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Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
359
Table 22. XISR – Xon–Xoff Interrupt Status Register
Bits 7:6
00 – none
10 – Xon received
11 – both received
11 – Illegal, does not occur
determine if the receiver has encountered an Xon or Xoff character
in the incoming data stream. These bits are maintained until a read
of the XISR. The field is updated by X character reception
regardless of the state of MR0(7, 3:2) or IMR(4). The field can
therefore be used as a character detector for the bit patterns stored
in the Xon and Xoff Character Registers.
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Bits 5:4
Automatic X Character
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Bits 3:2
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Bits 1:0
TxD character status
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00 – none
10 – Xoff transmitted
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00 – normal
10 – re–enabled
11 – flow disabled
WDT
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00 – normal TxD data
10 – Xoff in pending
11 – Xon in pending
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XISR[5:4] –
Automatic transmission Status. This field indicates the
last flow control character sent in the Auto Receiver flow control
mode. If Auto Receiver mode has not been enabled, this field will
always read b’00. It will likewise reset to b’00 if MR0(3) is reset. If
the Auto Receiver mode is exited while this field reads b’10, it is the
user’s responsibility to transmit an Xon, when appropriate.
XISR[3:2] –
TxD flow Status. This field tracks the transmitter’s flow
status as follows:
00 – normal. The flow control is under host control.
01 – TxD halt pending. After the current character finishes the
transmitter will stop. The status will then change to b’00.
10 – re–enabled. The transmitter had been halted and restarted.
It is sending data characters. After a read of the XISR, it will
return to ”normal” status.
11 – disabled. The transmitter is flow controlled.
XISR[1:0] –
TxD character Status. This field allows determination of
the type of character being transmitted. If XISR(1:0) is b’01, the
channel is waiting for a data character to transfer from the TxFIFO.
This condition will only occur for a bit time after an Xon or Xoff
character transmission unless the TxFIFO is empty.
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This register enables the watch-dog Timer for each of the 8
receivers on the Octal UART.
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–
BRG Timer Reload
Registers, Upper
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This is the upper byte of the 16 bit value used by the BRG timer in
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–
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8 LSB of the BRG Timer divisor.
This is the lower byte of the 16 bit value used by the BRG timer in
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Table 26. BRGTCR – BRG Timer Control Register (BRGTCR)
Bit 7
holds it stopped
001 – Sclk / 32
100 – X1
110 – I/O1b
IN
counters. The clock selection is for the input to the counters. It is
that clock divided by the number represented by the BRGTU and
BRGTL the will be used as the 16x clock for the receivers and
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Bit 6:4
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Bit 3
holds it stopped.
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Bit 2:0
001 – Sclk / 32
100 – X1
110 – I/O1a
IN
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run.
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run.
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consider it as a 16x clock and further device it by 16. In other words
the receivers and transmitters will always be in the 16x ode of
operation when the internal BRG timer is selected for their clock.
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threshold for use by the interrupt arbiter. The field is interpreted as a
single unsigned integer. The interrupt arbiter will not generate an
external interrupt request, by asserting IRQN, unless the value of
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threshold. If the highest bidder in the interrupt arbitration is lower
than the threshold level set by the ICR, the Current Interrupt
Register, CIR, will contain x’00. Refer to the functional description of
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