參數(shù)資料
型號(hào): SC68L198
廠(chǎng)商: NXP Semiconductors N.V.
英文描述: Octal UART with TTL compatibility at 3.3V and 5V supply voltages
中文描述: 八路與TTL兼容的UART在3.3V和5V電源電壓
文件頁(yè)數(shù): 21/49頁(yè)
文件大小: 358K
代理商: SC68L198
Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
356
Table 9. Command Register Code
Code
Command
CR[7:3]
Description
00011
Reset Transmitter
00100
Reset Error Status
01000
Assert RTSN (I/O2 or I/O1)
01001
Negate RTSN (I/O2 or I/O1)
01110
Reserved
01111
Reserved
áááááá
áááááá
ááááááááááááááááááááááááááááááááááá
áááááá
ááááááááááá
ááááááááááá
ááááááááááá
ááááááá
ááááááá
Code
CR[7:3]
10011
10100
11000
11001
11110
11111
ááááááá
áááááááááááááá
áááááááááááááá
Command
Description
Gang Write Xoff Character Registers *
Gang Load Xon Character Registers DC1 *
Cancel Transmit X Char command
Reserved
Reset All UART channel registers
Reset Device *
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
ááááááááááááááááááááááááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááááá
áááááááááááááá
áááááá
ááááááááááá
ááááá
ááááááá
ááááá
áááááááááááááá
áááááá
Break
0 – No
ááááá
ááááá
ááááá
ááááá
ááááá
ááááá
Error
0 – No
ááááá
ááááá
ááááá
ááááá
ááááá
áááááá
áááááá
ááááá
ááááá
ááááá
ááááá
ááááá
ááááá
ááááá
0 – No
ááááá
ááááá
ááááá
ááááá
ááááá
ááááá
0 – No
ááááá
ááááá
ááááá
0 – No
ááááá
áááááá
áááááá
0 – No
áááááá
ááááá
ááááá
0 – No
ááááá
ááááá
ááááá
0 – No
ááááá
ááááá
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received; further entries to the
FIFO are inhibited until the RxD line returns to the marking state for
at least one half bit time (two successive edges of the internal or
external 1x clock). When this bit is set, the change in break bit in
the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break
condition, as defined above, is detected. The break detect circuitry
is capable of detecting breaks that originate in the middle of a
received character. However, if a break begins in the middle of a
character, it must last until the end of the next character in order for
it to be detected.
ááááá
ááááá
ááááá
ááááá
ááááá
detect, parity error and framing error status, if any) is lost. This bit is
cleared by a reset error status command.
áááááá
ááááá
ááááá
SR[6] – Framing Error (FE)
This bit, when set, indicates that a stop bit was not detected when
the corresponding data character in the FIFO was received. The
stop bit check is made in the middle of the first stop bit position.
SR[5] – Parity Error (PE)
This bit is set when the ’with parity’ or ’force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity. In the special ’wake up mode’, the
parity error bit stores the received A/D bit.
SR[4] – Overrun Error (OE)
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the RxFIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
SR[3] – Transmitter Empty (TxEMT)
This bit is set when the transmitter underruns, i.e., both the TxFIFO
and the transmit shift register are empty.
It is set after transmission of the last stop bit of a character, if no
character is in the TxFIFO awaiting transmission. It is reset when
the TxFIFO is loaded by the CPU, or when the transmitter is
disabled.
SR[2] – Transmitter Ready (TxRDY)
This bit, when set, indicates that the TxFIFO is ready to be loaded
with a character. This bit is cleared when the TxFIFO is loaded by
the CPU and is set when the last character is transferred to the
transmit shift register. TxRDY is reset when the transmitter is
disabled and is set when the transmitter is first enabled, e.g.,
characters loaded in the TxFIFO while the transmitter is disabled will
not be transmitted.
SR[1] – RxFIFO Full (RxFULL)
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all sixteen RxFIFO positions are occupied. It is
reset when the CPU reads the RxFIFO and that read leaves one
empty byte position. If a character is waiting in the receive shift
register because the RxFIFO is full, RxFULL is not reset until the
second read of the RxFIFO since the waiting character is
immediately loaded to the RxFIFO.
相關(guān)PDF資料
PDF描述
SC68L198A1A Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 50 psi, Gage, flush mount with flange, 10 Vdc excitation
SC68L198C1A Octal UART with TTL compatibility at 3.3V and 5V supply voltages
SC28C94 Quad universal asynchronous receiver/transmitter QUART
SC28C94A1N Quad universal asynchronous receiver/transmitter QUART
SC28L194 Quad UART for 3.3V and 5V supply voltage(在3.3V和5V電源電壓中應(yīng)用的四 UART)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SC68L198A1A 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Octal UART with TTL compatibility at 3.3V and 5V supply voltages
SC68L198C1A 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Octal UART with TTL compatibility at 3.3V and 5V supply voltages
SC68PM302PV25B 制造商:Freescale Semiconductor 功能描述:
SC690AB00 制造商:Schneider Electric 功能描述:ULTRASONICPROXIMITYSENSOR 制造商:Schneider-Telemacanique 功能描述:ULTRASONICPROXIMITYSENSOR 制造商:SCHNEIDER ELECTRIC 功能描述:ULTRASONICPROXIMITYSENSOR
SC6946 功能描述:螺絲和緊固件 SHLDR SCREW SOCKET 10-32, STAIN STEEL RoHS:否 制造商:Unspecified 產(chǎn)品: 類(lèi)型:Washer 螺紋大小: 長(zhǎng)度: 材料:Steel 電鍍:Nickel 螺絲頭: 螺絲類(lèi)型: