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參數(shù)資料
| 型號(hào)： | SC3308Q/TD |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LVTTL SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 0.039 INCH PITCH, PLASTIC, QFP-52 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 115K |
| 代理商： | SC3308Q/TD |
Applied Micro Circuits Corporation
6290 Sequence Dr., San Diego, CA 92121-4358
6
SC3306/08
20-OUTPUT LVTTL CLOCK DRIVERS
DESCRIPTION OF OPERATION
(Refer to Logic Diagram)
AMCC has developed the clock drivers using an ad-
vanced BiCMOS process. This design has been opti-
mized for minimum skew across all twenty outputs.
For highest performance this approach requires a
clock source input from a crystal-controlled oscillator
(XCO) located adjacent to the clock driver. This
oscillator can provide either differential ECL inputs
(referenced to +5V, PECL) or TTL (CMOS) input levels
to the clock driver. The input selection is accom-
plished via the “Clock Sel” input where a “HIGH”
level activates the differential ECL input and a
“LOW” activates the TTL input. This input clock will
be fanned out to a toggle flip-flop or output flip-flops
for synchronization, refer to Logic Diagrams. Using
this methodology, the output duty cycle for the 1/2x
outputs becomes largely a function of output driver
slew rate into the AC load, and the duty cycle of the
1x outputs is a functions of the input clock wave-
shape and the output driver slew rate into the AC
load.
The RESET input is provided to hold off or clear the
outputs as may be required by the user’s system.
This pin may be logically driven from a TTL output.
Optionally, if a capacitor (4.7uF = ~100 ms) is con-
nected between this pin and ground, the device will
respond with a “power up reset”—a delay in the
clock outputs becoming active. At the onset of
RESET (low) the outputs will go low following four
falling-edge clock inputs. At the expiration of RESET
(high) outputs will resume, after four falling-edge
clock inputs, from a high (leading edge) count origin
(see Figure 5, Reset To Output Timing, in the Clock
Driver Application Note).
The output drivers are rise and fall slew rate controlled
to ~1.5V/ns to minimize noise and distortion resulting
from simultaneous switching of the 20 outputs. These
outputs also feature series termination to signifi-
cantly reduce the overshoot and undershoot of
non-terminated transmission lines. This will satisfy
printed circuit line impedances of 65–75 Ohms
terminated into 15 pF (two IC input package receiver
pins). When applications require large load capaci-
tance (>25pF with 50 Ohm P.C. board impedance)
and/or large peak voltage amplitudes, two adjacent
drivers may be paralleled, thereby halving the series
resistance and doubling the peak current (see the
Clock Driver Application Note for Spice models).
Power and ground are interdigitated with the outputs.
Of the 52 package pins, 22 are used for low impedance
on-chip power distribution. Due to the simultaneously
switching outputs, low impedance +VCC and ground
planes within the P.C. board are recommended, as
well as substantial decoupling capacitance (see the
Clock Driver Application Note for recommendations).
The IC package and die layouts are tightly coupled
to assure precise matching of all of the outputs.
Collectively, the resistance, inductance, and capaci-
tance of the package and wire bonding is managed
to ensure that the clock driver will exhibit skews
less than the specified maximum. A plastic 52-lead
quad flat pack with .039" lead pitch is employed
with an outer lead square footprint of approximately
0.7" per side.
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