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參數(shù)資料
| 型號(hào)： | SC3308Q/TD |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LVTTL SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 0.039 INCH PITCH, PLASTIC, QFP-52 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 115K |
| 代理商： | SC3308Q/TD |
Applied Micro Circuits Corporation
6290 Sequence Dr., San Diego, CA 92121-4358
4
SC3306/08
20-OUTPUT LVTTL CLOCK DRIVERS
AC Specifications—Using “AC Test/Evaluation Circuit”
VCC = +5.0V ± 5%, Ta = 0°C to +70°C, CLOAD = 10pF
ECL
DIFFERENTIAL
INPUTS
0.5ns
MINIMUM
Voh-0.3V
50%
± 10%
0.5ns
MINIMUM
Vol+0.3V
50%
±1 ns*
CLOCK
OUTPUT
+2.0V
+1.5V
+0.8V
T rise
T fall
1.35ns
1.5ns
NOTE: Trise and Tfall are “real load” dependent. The values indicated are for 6" of board
trace (70 Ohm) with a 10 pF capacitive load. See the Clock Driver Application Note.
*Applies only to divide-by-two outputs.
+0.8V
Threshold Crossing Characteristics
Parameter
SC3306
SC3308
Units
Maximum Skew Across All Outputs
Options:
Standard
–1
1.0
0.5
1.0
0.5
ns
Maximum Skew within an Output Group
0.25
ns
Maximum Output Duty Cycle Asymmetry at 1.5V
±1.0
—
ns
Maximum TTL Input Frequency
80
MHz
Maximum PECL Differential Input Frequency
80
MHz
Maximum Rising/Falling Edge Rate
1.35/1.5
ns
Notes:
1.
Skew is referenced to the rising and falling edges of all outputs.
2.
Output symmetry follows input symmetry for the 1X outputs.
3.
Asymmetry is defined as the deviation from a 50% duty cycle measured at 1.5V. Asymmetry will be
affected by voltage, temperature, and load (including the length of the PC trace).
4.
Typical skew derating factor for different loads is 50ps/pF at 1.5V threshold. For example, a 5pF load
difference equals a 250 ps skew difference.
5.
Edge rates are measured from 0.8V to 2.0V. Load consists of a 6" board trace (70 Ohm) with a 10 pF
capacitive load. See “AC Test/Evaluation Circuit.” Synchronous outputs may be paralleled for higher
loads. The maximum rising edge rate is specified at 5.0V and must be derated at 1.4ns/V for VCC <5.0V.
6.
Parameters guaranteed by design and characterization or tested.
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