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參數資料
| 型號： | SC3308Q/TD |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LVTTL SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 0.039 INCH PITCH, PLASTIC, QFP-52 |
| 文件頁數： | 1/9頁 |
| 文件大?。?/td> | 115K |
| 代理商： | SC3308Q/TD |
Applied Micro Circuits Corporation
6290 Sequence Dr., San Diego, CA 92121-4358
1
20-OUTPUT LVTTL CLOCK DRIVERS
SC3306/08
20-OUTPUT LVTTL CLOCK DRIVERS
DEVICE SPECIFICATION
FEATURES
20 clock outputs:
- Ten or twenty outputs (SC3308) at primary
frequency, up to 80 MHz
- Ten outputs at 1/2 primary frequency (SC3306)
All outputs are leading edge synchronized
to within
≤0.5 ns
Proprietary output drivers with:
- Complementary 24 mA peak outputs,
source and sink
-65–75
source series termination
- Dynamic drive adjustment to match load
conditions
- Edge rates less than 1.5 ns
Output levels comply with JEDEC LVTTL
standard
+5V Vcc supply
52 PQFP package
Minimizes the ground-bounce, overshoot,
and ringing problems often encountered
when using CMOS and Bipolar drivers
APPLICATIONS
Compatible with Intel’s Pentium and
Pentium Pro processors, and PowerPC
603/604 processors
PCI Bus clock distribution
Workstation and server systems with
high clock fanout
Datacom and Telecom networks
GENERAL DESCRIPTION
The SC3306 and SC3308 are precision low skew
clock drivers with 20 outputs. These employ a clock
input from a single-ended TTL or an ECL differen-
tial source operating between +5V and ground
(PECL). This reference frequency input is received
and distributed to divide-by-two or master-slave flip-
flops. The resultant output is distributed to the clock
output drivers. All outputs conform with JEDEC
LVTTL levels.
Applied Micro Circuits Corporation (AMCC) uses
proprietary complementary (source and sink) 24
mA peak output drivers. In addition to their drive
capability, these circuits provide “source (series)
termination” at the TTL outputs that minimize over/
undershoot without requiring on-board termination
networks. They are designed for a maximum output
slew rate of
≈1.5V/ns to minimize simultaneous out-
put-switching noise and distortion.
SC3306 Logic Diagram
RESET
CLOCK SEL
20K
+5V
5
PECL
TTL
R
M
U
X
S - R
TFF
MS
FF
TA
F/2
TA
LVTTL
DRIVER
Fb5–9
Fb0–4
Fa5–9
Fa0–4
LVTTL
DRIVER
LVTTL
DRIVER
LVTTL
DRIVER
+5V
GND
DELAY
MATCHING
5
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