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參數(shù)資料
| 型號： | SC28C94 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Quad universal asynchronous receiver/transmitter QUART |
| 中文描述： | 四通用異步接收器/發(fā)送器夸脫 |
| 文件頁數(shù)： | 26/38頁 |
| 文件大?。?/td> | 230K |
| 代理商： | SC28C94 |
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Philips Semiconductors
Product specification
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
1998 Aug 19
26
AC ELECTRICAL CHARACTERISTICS
4
V
CC
= 5V
±
10%, T
A
= –40 C to 85 C, unless otherwise specified.
NO.
FIGURE
CHARACTERISTIC
LIMITS
Typ
UNIT
Min
10
45
Max
1
2
3
4
6
6
6
6
Setup: A[5:0] valid to CEN Low
Hold: A[5:0] valid after CEN Low
6
Access: Later of CEN Low and RDN Low, to Dnn valid (read)
Later of CEN Low and (RDN or WRN as applicable) Low, to DACKN Low
Normal Operation:
ns
ns
ns
ns
110/115
10 + 2
X1 edges
5
90/122 + 3
X1 edges
5
150
30
30
From Power Down:
Earlier of CEN High or RDN High, to Dnn released (read)
1
Earlier of CEN High or (RDN or WRN as applicable) High, to DACKN released
Earlier of CEN High or (RDN or WRN as applicable) High, in one cycle, to later
of CEN Low and (RDN or WRN as applicable) Low, for the next cycle
Setup, Dnn valid (write) to later of CEN Low and WRN Low
2
Later of CEN Low and WRN Low, to earlier of CEN High or WRN High
Hold: Dnn valid (write) after DACKN Low, CEN High or WRN High
3
5
6
6
6
0
0
ns
ns
7
6
50
ns
8
9
10
6
6
6
–30
ns
ns
ns
110/115
0
NOTES:
1. The minimum time indicates that read data will remain valid until the bus master drives CEN and/or RDN to High.
2. The fact that this parameter is negative means that the Dnn line may actually become valid after CEN and WRN are both Low.
3. In a Write operation, the bus master must hold the write data valid either until drives CEN and/or WRN to High, or until the QUART drives
DACKN to Low, whichever comes first.
4. Test condition for interrupt and I/O outputs: C
L
= 50pF, forced current for V
OL
= 4.0mA; forced current for V
OH
= 400
μ
A, RL = 2.7k
to V
CC
.
Test condition for rest of outputs: C
= 150pF
5. Consecutive write operations to the upper four bits of the Command Register (CR) require at least three X1/CLK edges; four X1/CLK edges
in the ‘X1/CLK divide by 2 edges’ according to register 2E or 2F setting.
6. Address is latched at leading edge of a read or write cycle.
A[5:0]
CEN
RDN
WRN
D[7:0]
1
2
1
2
READ CYCLE
WRITE CYCLE
DACKN
4
4
3
3
7
7
9
9
7
7
9
9
5
5
6
6
8
8
4
4
10
10
10
6
6
SD00677
X1/CLK
Figure 6. A Read Cycle Followed by a Write Cycle with DACKN
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| SC28C94A1A | 功能描述:UART 接口集成電路 UART QUAD W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC28C94A1A,512 | 功能描述:UART 接口集成電路 UART QUAD W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC28C94A1A,518 | 功能描述:UART 接口集成電路 5V 4 CH UART IND TEMP RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC28C94A1A | 制造商:NXP Semiconductors 功能描述:IC CMOS QUART SMD 28C94 PLCC52 |
| SC28C94A1A512 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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