參數(shù)資料
型號： SC28C94
廠商： NXP Semiconductors N.V.
英文描述： Quad universal asynchronous receiver/transmitter QUART
中文描述： 四通用異步接收器/發(fā)送器夸脫
文件頁數(shù)： 24/38頁
文件大?。?/td> 230K
代理商： SC28C94
Philips Semiconductors
Product specification
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
1998 Aug 19
24
AC ELECTRICAL CHARACTERISTICS
1, 2, 3, 4
V
CC
= 5V
±
10%, T
A
= –40 C to 85 C, unless otherwise specified.
SYMBOL
FIGURE
PARAMETER
LIMITS
Typ
UNIT
Min
Max
Reset timing
t
RES
I/O Port timing
t
PS
t
PH
11
Reset pulse width
200
ns
12
12
I/O input setup time before RDN Low
I/O input hold time after RDN High
I/O output valid from
WRN High (WRN or CEN high, whichever occurs first)
RDN Low (RDN or CEN low, whichever occurs last)
0
0
ns
ns
t
PD
12
40
40
ns
ns
Interrupt timing
t
IR
13
IRQN negated or I/O output High from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (break change interrupt)
Reset command (I/O change interrupt)
Stop C/T command (counter interrupt)
Write IMR (clear of interrupt mask bit)
With respect to a
3.6864MHz clock
on pin X1/CLK
80
80
80
80
80
80
ns
ns
ns
ns
ns
ns
Clock timing
t
CLK
t
CLK
t
CLK5
t
CTC
f
CTC5
t
RX
14
14
14
14
14
14
X1/CLK low/high time
X1/CLK low/high time (above 4MHz; X1/CLK
÷
2 active)
X1/CLK frequency
Counter/timer clock high or low time
Counter/timer clock frequency
RxC high or low time
RxC frequency (16X)
RxC frequency (1X)
TxC high or low time
TxC frequency (16X)
TxC frequency (1X)
125/100
56/56
0
60
0
30
0
0
30
0
0
ns
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
3.6864
8.0
8
f
RX5
14
16
1.0
t
TX
14
f
TX5
14
16
1.0
Transmitter timing
t
TXD
t
TCS
Receiver timing
t
RXS
t
RXH
NOTES:
1. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 20ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of V
IL
and V
IH
, as
appropriate.
2. Typical values are at +25
o
C, typical supply voltages, and typical processing parameters.
3. Test condition for interrupt and I/O outputs: C
= 50pF, R
= 2.7k
to V
. Test conditions for rest of outputs: C
= 150pF.
4. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
5. The minimum value is not tested, but is guaranteed by design. For t
CLK
minimum test rate is 2.0MHz.
15
15
TxD output delay from TxC low
TxC output delay from TxD output data
70
+10
ns
ns
–10
16
16
RxD data setup time to RxC high
RxD data hold time from RxC high
60
60
5
5
ns
ns
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