參數(shù)資料
型號(hào): SC28C94
廠商: NXP Semiconductors N.V.
英文描述: Quad universal asynchronous receiver/transmitter QUART
中文描述: 四通用異步接收器/發(fā)送器夸脫
文件頁(yè)數(shù): 25/38頁(yè)
文件大?。?/td> 230K
代理商: SC28C94
Philips Semiconductors
Product specification
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
1998 Aug 19
25
AC ELECTRICAL CHARACTERISTICS
1
V
CC
= 5V
±
10%, T
A
= –40 C to 85 C, unless otherwise specified.
NO.
FIGURE
CHARACTERISTIC
LIMITS
Typ
UNIT
Min
0
45
0
0
65
Max
1
2
3
4
5
6
7
8
9
10
5
5
5
5
5
5
5
5
5
5
A[5:0] Setup time to RDN WRN Low
A[5:0] Hold time from RDN WRN Low
CEN Setup time to RDN WRN Low
2
CEN Hold time from RDN WRN High
2
RDN WRN Pulse Width Low
D[7:0] Data Valid after CEN and RDN Low
D[7:0] Data Bus floating after RDN or CEN High
D[7:0] Data Bus Setup time before WRN or CEN High
D[7:0] Hold time after WRN or CEN High
Time between Reads and/or Writes
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
65
10
5
0
20
NOTES:
1. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
supply range.
2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as a ‘strobing’ input. CEN and
RDN (also CEN and WRN) are ANDed internally. As a consequence the signal asserted last initiates the cycle; the signal negated first
terminates the cycle. Address is latched at leading edge of a read or write cycle.
3. The RDN signal must be negated for this time to guarantee that internal registers update before the next read.
A[5:0]
CEN
RDN
WRN
D[7:0]
1
2
1
2
10
5
7
READ CYCLE
WRITE CYCLE
3
5
6
4
8
9
SD00164
Figure 5. A Read Cycle Followed by a Write Cycle without DACKN
相關(guān)PDF資料
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