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| 型號： | SC26L198A1A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
| 中文描述： | 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 25/49頁 |
| 文件大?。?/td> | 358K |
| 代理商： | SC26L198A1A |
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Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
360
interrupt generation for details on how the various interrupt source
bid values are calculated.
Note: While a watch-dog Timer interrupt is pending, the ICR is not
used and only receiver codes are presented for interrupt arbitration.
This allows receivers with very low count values (perhaps below the
threshold value) to win interrupt arbitration without requiring the user
to explicitly lower the threshold level in the ICR. These bits are the
upper seven (7) bits of the interrupt arbitration system. The lower
three (3) bits represent the channel number.
UCIR – Update CIR
A command based upon a decode of address x’8C. ( UCIR is not a
register!) A write (the write data is not important; a “don’t care”) to
this ’register’ causes the Current Interrupt Register to be updated
with the value that is winning interrupt arbitration. The register
would be used in systems that poll the interrupt status registers
rather than wait for interrupts. Alternatively, the CIR is normally
updated during an Interrupt Acknowledge Bus cycle in interrupt
driven systems.
00 – other
000 – no interrupt
Recognition
100 – Not used
01 – Transmit
11– Receive w/
10 – Receive w/o
.
5 => 14 characters
7 => 16
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000 = a
011 = d
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Current count code
0 => 9 or less
1 => 10 characters
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000 = a
001 = b
011 = d
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111 = h
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The Current Interrupt Register is provided to speed up the
specification of the interrupting condition in the Octal UART. The
CIR is updated at the beginning of an interrupt acknowledge bus
cycle or in response to an Update CIR command. (see immediately
above) Although interrupt arbitration continues in the background,
the current interrupt information remains frozen in the CIR until
another IACKN cycle or Update CIR command occurs. The LSBs of
the CIR provide part of the addressing for various Global Interrupt
registers including the GIBCR, GICR, GITR and the Global RxFIFO
and TxFIFO FIFO. The host CPU need not generate individual
addresses for this information since the interrupt context will remain
stable at the fixed addresses of the Global Interrupt registers until
the CIR is updated. For most interrupting sources, the data
available in the CIR alone will be sufficient to set up a service
routine.
The CIR may be processed as follows:
If CIR[7] = 1, then a receiver interrupt is pending and the count is
CIR[5:3], channel is CIR[2:0]
Else If CIR[6] = 1 then a transmitter interrupt is pending and the
count is CIR[5:3], channel is CIR[2:0]
Else the interrupt is another type, specified in CIR[5:3]
Note: The GIBCR, Global Interrupting Byte Count Register, may be
read to determine an exact character count if 9 or less characters
are indicated in the count field of the CIR.
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The IVR contains the byte that will be placed on the data bus during
an IACKN cycle when the GCCR bits (2:1) are set to binary ‘01’.
This is the unmodified form of the interrupt vector.
Always contains
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Will be replaced
interrupt type if IVC
field of GCCR > 1
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Replaced with
number if IVC field of
GCCR > 0
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interrupting source. The modification of the IVR as it is presented to
the data bus during an IACK cycle is controlled by the setting of the
bits (2:1) in the GCCR (Global Chip Configuration Register)
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Bits 7:3
Reserved
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Bits 2:0
Channel code
100 = e
110 = g
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A register associated with the interrupting channel as defined in the
CIR. It contains the interrupting channel code for all interrupts.
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000 = a
010 = c
Bits 7:4
Reserved
Channel byte count code
0001 = 2
.
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Bits 3:0
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A register associated with the interrupting channel as defined in the
CIR. Its numerical value equals
the number of bytes minus 1 (count – 1) ready for transfer to the
transmitter or transfer from the receiver. It is undefined for other
types of interrupts
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