參數(shù)資料
型號： SC26L198A1A
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Octal UART with TTL compatibility at 3.3V and 5V supply voltages
中文描述： 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84
封裝： PLASTIC, LCC-84
文件頁數(shù)： 19/49頁
文件大?。?/td> 358K
代理商： SC26L198A1A
Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
354
Table 7. Data Clock Mux
CCLK = 3.6864 MHz
00000
BRG – 50
00100
BRG – 300
00101
BRG – 450
01001
BRG – 1800
01010
BRG – 2400
01111
BRG – 14.4K
Table 8. CR – Command Register
CR is used to write commands to the Octal UART.
Command
Register Table”
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10000
10100
10101
11001
11010
11111
The encoded value of this field can be used to specify a single
command as follows:
00000
No command.
00001
Reserved
00010
Reset receiver. Resets the receiver as if a hardware reset
had been applied. The receiver is disabled and the FIFO
pointer is reset to the first location effectively discarding all
unread characters in the FIFO.
00011
Reset transmitter. Resets the transmitter as if a hardware
reset had been applied.
00100
Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status register
(SR[7:4]). Used in character mode to clear overrun error
status (although RB, PE and FE bits will also be cleared),
and in block mode to clear all error status after a block of
data has been received.
00101
Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2]) to be
cleared to zero.
00110
Start break. Forces the TxD output low (spacing). If the
transmitter is empty, the start of the break condition will be
delayed up to two bit times. If the transmitter is active, the
break begins when transmission of the current character
is completed. If there are characters in the TxFIFO, the
start of break is delayed until those characters, or any
others loaded after it have been transmitted (TxEMT must
be true before break begins). The transmitter must be
enabled to start a break.
00111
Stop break. The TxD line will go high (marking) within two
bit times. TxD will remain high for one bit time before the
next character, if any, is transmitted.
01000
Assert RTSN. Causes the RTSN output to be asserted
(low).
01001
Negate RTSN. Causes the RTSN output to be negated
(high).
Note: The two commands above actually reset and
set, respectively, the I/O2 or I/O1 pin associated with
the I/OPIOR register.
01010
Reserved
01011
Reserved
01100
Reserved
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CCLK = 3.6864 MHz
BRG – 19.2K
BRG – 115.2K
BRG – 230.4K
IN
BRG C/T 1
Reserved
Reserved
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CR[2] – Lock TxD and RxFIFO enables
If set, the transmitter and receiver enable bits, CR[1:0] are not
significant. The enabled/disabled state of a receiver or transmitter
can be changed only if this bit is at zero during the time of the write
to the command register.
WRITES TO THE UPPER BITS OF THE
CR WOULD USUALLY HAVE CR[2] AT 1
to maintain the condition
of the receiver and transmitter. The bit provides a mechanism for
writing commands to a channel, via CR[7:3], without the necessity of
keeping track of or reading the current enable status of the receiver
and transmitter.
CR[1] – Enable Transmitter
A one written to this bit enables operation of the transmitter. The
TxRDY status bit will be asserted. When disabled by writing a zero
to this bit, the command terminates transmitter operation and resets
the TxRDY and TxEMT status bits. However, if a character is being
transmitted or if characters are loaded in the TxFIFO when the
transmitter is disabled, the transmission of the all character(s) is
completed before assuming the inactive state.
CR[0] – Enable Receiver
A one written to this bit enables operation of the receiver. If not in
the special wake up mode, this also forces the receiver into the
search for start bit state. If a zero is written, this command
terminates operation of the receiver immediately – a character being
received will be lost. The command has no effect on the receiver
status bits or any other control registers. If the special wake–up
mode is programmed, the receiver operates even if it is disabled
(see Wake–up Mode).
CR[7:3] – Miscellaneous Commands
( See Table below)
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