參數(shù)資料
型號: SC26C198A1A
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Octal UART with TTL compatibility at 3.3V and 5V supply voltages
中文描述: 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84
封裝: PLASTIC, LCC-84
文件頁數(shù): 37/49頁
文件大?。?/td> 358K
代理商: SC26C198A1A
Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
372
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A(7:0)
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Read
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UART G
Receiver FIFO Reg g (RxFIFOg)
Input Port Reg g (IPRg)
Reserved
Reserved
Reserved
11101110 (xEE)
Reserved
11101111 (xEF)
Reserved
Write
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11100011 (xE3)
11100100 (xE4)
11101000 (xE8)
11101001 (xE9)
11101101 (xED)
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Transmitter FIFO Reg g (TxFIFOg)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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11110001 (xF1)
11110010 (xF2)
11110110 (xF6)
11110111 (xF7)
11111011 (xFB)
11111100 (xFC)
11111101 (xFD)
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Status Register h (SRh)
Interrupt Status Register h (ISRh)
Xon/XoffInterrupt Status Reg h (XISRh)
Reserved
Reserved
Reserved
Reserved
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Command Register h (CRh)
Interrupt Mask Register h (IMRh)
Reserved
Reserved
Reserved
Reserved
Reserved
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Device Configuration after Hardware Reset or CRa
cmd=x1F
Cleared registers:
Channel Status Registers (SR)
Channel Interrupt Status Registers (ISR)
Channel Interrupt Mask Registers (IMR)
Channel Interrupt Xon Status Register (XISR)
Interrupt Control Register (ICR)
Global Configuration Control Register (GCCR)
Hence the device enters the asynchronous bus cycling mode.
Current Interrupt Register (CIR)
BRG Timer Run Control Register (BRGTCR)
Watch-dog Timer Run Control Register (WDTRCR)
Channel Input/Output Port Configuration Registers (I/OPCR)
Hence all I/O pins have direction = Input after reset
Clears Modes for:
Power down
Test modes
Input Port Changed bits
Gang write to Xon or Xoff
Xon/Xoff/Address detection
Receiver error status
Disables:
Transmitters
Receivers
Interrupts, current and future
Halts:
BRG Counters
Bus cycle in progress (hardware RESET only)
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