參數(shù)資料
型號(hào)： SC26C198A1A
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： Octal UART with TTL compatibility at 3.3V and 5V supply voltages
中文描述： 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84
封裝： PLASTIC, LCC-84
文件頁(yè)數(shù)： 23/49頁(yè)
文件大?。?/td> 358K
代理商： SC26C198A1A
Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
358
IMR[7] –
Controls if a change of state in the inputs equipped with
input change detectors will cause an interrupt.
IMR[6] –
Controls the generation of an interrupt by the watch-dog
timer event. If set, a count of 64 idle bit times in the receiver will
begin interrupt arbitration.
IMR[5] –
Enables the generation of an interrupt in response to
changes in the Address Recognition circuitry of the Special Mode
IMR[4] –
Enables the generation of an interrupt in response to
recognition of an in–band flow control character.
IMR[3] –
Reserved
IMR[2] –
Enables the generation of an interrupt when a Break
condition has been detected by the channel receiver.
IMR[1] –
Enables the generation of an interrupt when servicing for
the RxFIFO is desired.
IMR[0] –
Enables the generation of an interrupt when servicing for
the TxFIFO is desired.
Received
status of each byte received is stored with that byte and is moved
along with the byte as the characters are read from the FIFO. The
upper three bits are presented in the STATUS register and they
change in the status register each time a data byte is read from the
FIFO. Therefor the status register should be read BEFORE the byte
is read from the RxFIFO if one wishes to ascertain the quality of the
byte
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MSBs =0 for 7,6,5 bit
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The forgoing applies to the ”character error” mode of status
reporting. See MR1[5] and ”RxFIFO Status” descriptions for ”block
error” status reporting. Briefly ”Block Error” gives the accumulated
error of all bytes received in the RxFIFO since the last “Reset Error”
command was issued. (CR = x’04)
Table 14. TxFIFO – Transmitter FIFO
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Bits 7:0
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8 data bits. MSBs set to 0 for 7, 6, 5 bit data
character lengths less than 8 bits the upper bits will be ignored by
the transmitter state machine and thus are effectively discarded.
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Bits 7:3
Reserved
MSB of break change interrupt bid
This register provides the 3 MSBs of the Interrupt Arbitration number
for a break change interrupt.
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Bits 2:0
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Table 16. BCRCOS – Bidding Control Register –
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This register provides the 3 MSBs of the Interrupt Arbitration number
for a Change of State, COS, interrupt.
for an Xon/Xoff interrupt.
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Table 18. BCRA – Bidding Control Register –
Reserved
MSB of an address recognition event
for an address recognition event interrupt.
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Xon character.
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An 8 bit character register that contains the compare value for an
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Bits 7:0
8 Bits of the Multi–Drop Address Character Recognition
wake–up address character
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