- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372122 > SC26C198A1A (NXP SEMICONDUCTORS) Octal UART with TTL compatibility at 3.3V and 5V supply voltages PDF資料下載
參數(shù)資料
| 型號： | SC26C198A1A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
| 中文描述： | 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 16/49頁 |
| 文件大?。?/td> | 358K |
| 代理商： | SC26C198A1A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
REGISTER DEFINITIONS
The operation of the Octal UART is programmed by writing control
words into the appropriate registers. Operational feedback is
provided via status registers which can be read by the host CPU.
The Octal UART addressing is loosely divided, by the address bit
A(7), into two parts:
1) That part which is concerned with the configuration of the chip
interface and communication modes.
This part controls the elements of host interface setup, interrupt
arbitration, I/O Port Configuration that part of the UART channel
definitions that do not change in normal data handling. This section
is listed in the ”Register Map, Control”.
2) That part concerned with the transmission and reception of the bit
streams.
This part concerns the data status, FIFO fill levels, data error
conditions, channel status, data flow control (hand shaking). This
section is listed in the ”Register Map, Data”.
The Global Configuration Control Register (GCCR) sets the type of
bus cycle, interrupt vector modification and the power up or down
mode.
Table 2. GCCR – Global Configuration Control Register
THIS IS A VERY IMPORTANT REGISTER! IT SHOULD BE THE FIRST REGISTER ADDRESSED DURING INITIALIZATION
.
1 – Sync,
áááááá
áááááá
áááááá
áááááá
ááááááá
ááááááá
ááááááá
ááááááá
ááááááá
ááááá
ááááá
ááááá
ááááá
ááááá
áááááááááááá
áááááááááááá
áááááááááááá
01 – IVR
11 – IVR + interrupt type + channel code
transmission/reception activities cease, and all processing for input
recognition is disabled.
áááááááááááá
áááááááá
áááááááá
1 – Power down
áááááááá
áááááá
ááááááá
ááááá
áááááááááááá
áááááááááááá
áááááááá
áááááááá
áááááá
áááááá
GCCR(7):
This bit is reserved for future versions of this device. If
áááááá
ááááááá
ááááááá
ááááááá
ááááá
ááááá
ááááá
áááááááááááá
áááááááááááá
áááááááááááá
áááááááá
áááááááá
áááááááá
GCCR(6):
Bus cycle selection
Controls the operation of the host interface logic. If reset, the power
on/reset default, the host interface can accommodate arbitrarily long
bus I/O cycles. If the bit is set, the Octal UART expects four Sclk
cycle bus I/O operations similar to those produced by an i80386
processor in non–pipelined mode. The major differences in these
modes are observed in the DACKN pin function. In Sync mode, no
negation of CEN is required between cycles.
GCCR(2:1):
Interrupt vector configuration
The IVC field controls if and how the assertion of IACKN (the
interrupt acknowledge pin) will form the interrupt vector for the Octal
UART. If b’00, no vector will be presented during an IACKN cycle.
The bus will be driven high (xFF). If the field contains a b’01, the
contents of the IVR, Interrupt Vector Register, will be presented as
the interrupt vector without modification. If IVC = b’10, the channel
code will replace the 3 LSBs of the IVR; if IVC = b’11 then a modified
interrupt type and channel code replace the 5 LSBs of the IVR.
Note: The modified type field IVR(4:3) is:
10
Receiver w/o error
11
Receiver with error
01
Transmitter
00
All remaining sources
GCCR(0):
Power down control
Controls the power down function. During power down the internal
transparency
0 – flow control characters
the
1 – Address characters
Note: For maximum power savings it is recommended that all
switching inputs be stopped and all input voltage levels be within 0.5
volt of the Vcc and Vss power supply levels.
To switch from the asynchronous to the synchronous bus cycle
mode, a single write operation to the GCCR, terminated by a
negation of the CEN pin, is required. This cycle may be 4 cycles
long if the setup time of the CEN edge to Sclk can be guaranteed.
The host CPU must ensure that a minimum of two Sclk cycles
elapse before the initiation of the next (synchronous) bus cycle(s).
A hardware or software reset is recommended for the unlikely
requirement of returning to the asynchronous bus cycling mode.
MR – Mode Registers
The user must exercise caution when changing the mode of running
receivers, transmitters or BRG counter/timers. The selected mode
will be activated immediately upon selection, even if this occurs
during the reception or transmission of a character. It is also
possible to disrupt internal controllers by changing modes at critical
times, thus rendering later transmission or reception faulty or
impossible. An exception to this policy is switching from auto–echo
or remote loop back modes to normal mode. If the deselection
occurs just after the receiver has sampled the stop bit (in most
cases indicated by the assertion of the channel’s RxRDY bit) and
the transmitter is enabled, the transmitter will remain in auto–echo
áááááááá
áááááááá
áááááááááááááááááááááááááááááááááá
ááááááá
ááááááá
ááááááá
áááááá
áááááá
áááááááááá
áááááááááá
ááááááá
ááááááá
control
00 – none
10 – Auto doze
ááááááá
áááááááá
ááááááá
0 – Address characters
RxFIFO
áááááá
TxFIFO
level
01 – 3/4 empty
11 – not full
áááááááááá
00 – host mode, only the host CPU
through the CR
11 – Auto Receiver and Transmitter
ááááááá
áááááááá
áááááááá
áááááááá
áááááááááááááááááááááááááááááááááá
onto the RxFIFO
áááááááá
áááááááá
áááááááá
ááááááá
ááááááá
ááááááá
ááááááá
ááááááá
áááááá
áááááá
áááááá
áááááá
áááááá
áááááá
áááááááááá
áááááááááá
áááááááááá
áááááááááá
áááááááááá
áááááááááá
ááááááá
ááááááá
ááááááá
ááááááá
ááááááá
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC26C198C1A | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
| SC68C198 | Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 50 psi, Absolute, Cell with body o-ring, 10 Vdc excitation |
| SC68C198A1A | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
| SC68C198C1A | Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 50 psi, Absolute, flush mount, 10 Vdc excitation |
| SC68L198 | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC26C198C1A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
| SC26C562 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS dual universal serial communications controller CDUSCC |
| SC26C562_06 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS dual universal serial communications controller (CDUSCC) |
| SC26C562A8A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:CMOS dual universal serial communications controller CDUSCC |
| SC26C562C1A | 制造商:PHILIPS-SEMI 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。