參數(shù)資料
型號： SC16IS762IPW-T
廠商： NXP Semiconductors
文件頁數(shù)： 30/60頁
文件大?。?/td> 0K
描述： IC UART DUAL I2C/SPI 28-TSSOP
標(biāo)準(zhǔn)包裝： 2,500
特點： 低電流
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.5V, 3.3V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
配用： 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
36 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter. When designing a system, it is necessary to take into account cases when
acknowledge is not received. This happens, for example, when the addressed device is
busy in a real-time operation. In such a case the master, after an appropriate ‘time-out’,
should abort the transfer by generating a STOP condition, allowing other transfers to take
place. These ‘other transfers’ could be initiated by other masters in a multimaster system,
or by this same master.
There are two exceptions to the ‘a(chǎn)cknowledge after every byte’ rule. The first occurs when
a master is a receiver: it must signal an end of data to the transmitter by not signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.
The second exception is that a slave will send a negative acknowledge when it can no
longer accept additional data bytes. This occurs after an attempted transfer that cannot be
accepted.
Fig 14. Data transfer on the I2C-bus
S
P
SDA
SCL
MSB
0
1
6
7
8
0
1
2 to 7
8
ACK
002aab012
START
condition
STOP
condition
acknowledgement signal
from receiver
byte complete,
interrupt within receiver
clock line held LOW
while interrupt is serviced
Fig 15. Acknowledge on the I2C-bus
S
01
6
7
8
002aab013
data output
by transmitter
data output
by receiver
SCL from master
START
condition
transmitter stays off of the bus
during the acknowledge clock
acknowledgement signal
from receiver
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SC16IS850LIBS,151 功能描述:UART 接口集成電路 UART/12C-BUS/ SPI INTERF.128 FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16IS850LIBS,157 功能描述:UART 接口集成電路 UART/12C-BUS/ SPI INTERF.128 FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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SC16IS850LIPW,128 制造商:NXP Semiconductors 功能描述:SC16IS850LIPW/TSSOP24/RAIL13T// - Tape and Reel 制造商:NXP Semiconductors 功能描述:Slave I2C-bus/SPI Interface, 128 bytes
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