參數(shù)資料
型號: SC16IS762IPW-T
廠商: NXP Semiconductors
文件頁數(shù): 27/60頁
文件大小: 0K
描述: IC UART DUAL I2C/SPI 28-TSSOP
標準包裝: 2,500
特點: 低電流
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.5V, 3.3V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 28-TSSOP
包裝: 帶卷 (TR)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
33 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.21 Enhanced Features Register (EFR)
This 8-bit register enables or disables the enhanced features of the UART. Table 31
shows the Enhanced Features Register bit settings.
9.
RS-485 features
9.1 Auto RS-485 RTS control
Normally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the
logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR
register bit 4 will take the precedence over the other two modes; once this bit is set, the
transmitter will control the state of the RTS pin. The transmitter automatically asserts the
RTS pin (logic 0) once the host writes data to the transmit FIFO, and de-asserts RTS pin
(logic 1) once the last bit of the data has been transmitted.
To use the auto RS-485 RTS mode the software would have to disable the hardware flow
control function.
9.2 RS-485 RTS output inversion
EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.
When the transmitter has data to be sent it de-asserts the RTS pin (logic 1), and when the
last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).
Table 31.
Enhanced Features Register bits description
Bit
Symbol
Description
7
EFR[7]
CTS flow control enable.
logic 0 = CTS flow control is disabled (normal default condition)
logic 1 = CTS flow control is enabled. Transmission will stop when a
HIGH signal is detected on the CTS pin.
6
EFR[6]
RTS flow control enable.
logic 0 = RTS flow control is disabled (normal default condition)
logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when
the receiver FIFO halt trigger level TCR[3:0] is reached, and goes
LOW when the receiver FIFO resume transmission trigger level
TCR[7:4] is reached.
5
EFR[5]
Special character detect.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. Received data is compared
with Xoff2 data. If a match occurs, the received data is transferred to
FIFO and IIR[4] is set to a logical 1 to indicate a special character has
been detected.
4
EFR[4]
Enhanced functions enable bit.
logic 0 = disables enhanced functions and writing to IER[7:4],
FCR[5:4], MCR[7:5].
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and
MCR[7:5] so that they can be modified.
3:0
EFR[3:0]
Combinations of software flow control can be selected by programming
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