參數(shù)資料
型號: SC16IS760IPW
廠商: NXP Semiconductors N.V.
元件分類: 連接器件
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁數(shù): 27/62頁
文件大小: 308K
代理商: SC16IS760IPW
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
27 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.6 Modem Control Register (MCR)
The MCR controls the interface with the mode, data set, or peripheral device that is
emulating the modem.
Table 17
shows the Modem Control Register bit settings.
[1]
MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.
[2]
Only available on SC16IS750/SC16IS760.
Table 17.
Bit
7
Modem Control Register bits description
Symbol
Description
MCR[7]
[1]
clock divisor
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
MCR[6]
[1]
IrDA mode enable
logic 0 = normal UART mode
logic 1 = IrDA mode
MCR[5]
[1]
Xon Any
logic 0 = disable Xon Any function
logic 1 = enable Xon Any function
MCR[4]
enable loopback
logic 0 = normal operating mode
logic 1 = enable local Loopback mode (internal). In this mode the
MCR[1:0] signals are looped back into MSR[4:5] and the TX output is
looped back to the RX input internally.
MCR[3]
reserved
MCR[2]
TCR and TLR enable
logic 0 = disable the TCR and TLR register.
logic 1 = enable the TCR and TLR register.
MCR[1]
RTS
logic 0 = force RTS output to inactive (HIGH)
logic 1 = force RTS output to active (LOW). In Loopback mode,
controls MSR[4]. If Auto RTS is enabled, the RTS output is controlled
by hardware flow control.
MCR[0]
DTR
[2]
. If GPIO5 is selected as DTR modem pin through IOControl
register bit 1, the state of DTR pin can be controlled as below. Writing to
IOState bit 5 will not have any effect on this pin.
logic 0 = Force DTR output to inactive (HIGH)
logic 1 = Force DTR output to active (LOW)
6
5
4
3
2
1
0
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