參數(shù)資料
型號(hào)： SC16IS760IPW
廠商： NXP Semiconductors N.V.
元件分類(lèi)： 連接器件
英文描述： Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝： SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁(yè)數(shù)： 24/62頁(yè)
文件大小： 308K
代理商： SC16IS760IPW
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
24 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1]
FIFO reset requires at least two XTAL1 clocks, therefore, they cannot be reset without the presence of the
XTAL1 clock.
8.4 Line Control Register (LCR)
This register controls the data communication format. The word length, number of stop
bits, and parity type are selected by writing the appropriate bits to the LCR.
Table 12
shows the Line Control Register bit settings.
Table 12.
Bit
7
Line Control Register bits description
Symbol
Description
LCR[7]
divisor latch enable
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
LCR[6]
Break control bit. When enabled, the break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition).
logic 1 = forces the transmitter output (TX) to a logic 0 to alert the
communication terminal to a line break condition
LCR[5]
Set parity. LCR[5] selects the forced parity format (if LCR[3] = 1).
logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data.
LCR[4]
parity type select
logic 0 = odd parity is generated (if LCR[3] = 1)
logic 1 = even parity is generated (if LCR[3] = 1)
LCR[3]
parity enable
logic 0 = no parity (normal default condition).
logic 1 = a parity bit is generated during transmission and the receiver
checks for received parity
LCR[2]
Number of stop bits. Specifies the number of stop bits.
0 to 1 stop bit (word length = 5, 6, 7, 8)
1 to 1.5 stop bits (word length = 5)
1 = 2 stop bits (word length = 6, 7, 8)
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received; see
Table 15
.
6
5
4
3
2
1:0
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