參數(shù)資料
型號(hào): SC16IS750IBS
廠商: NXP Semiconductors N.V.
元件分類: 連接器件
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁數(shù): 33/62頁
文件大?。?/td> 308K
代理商: SC16IS750IBS
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
33 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.15 Receiver FIFO Level register (RXLVL)
This register is a read-only register, it reports the fill level of the receive FIFO. That is, the
number of characters in the RX FIFO.
8.16 Programmable I/O pins Direction register (IODir)
This register is only available on the SC16IS750 and SC16IS760. This register is used to
program the I/O pins direction. Bit 0 to bit 7 controls GPIO0 to GPIO7.
Remark:
If there is a pending input (GPIO) interrupt and IODir is written, this pending
interrupt will be cleared, that is, the interrupt signal will be negated.
8.17 Programmable I/O pins State Register (IOState)
This register is only available on the SC16IS750 and SC16IS760. When ‘read’, this
register returns the actual state of all I/O pins. When ‘write’, each register bit will be
transferred to the corresponding IO pin programmed as output.
8.18 I/O Interrupt Enable Register (IOIntEna)
This register is only available on the SC16IS750 and SC16IS760. This register enables
the interrupt due to a change in the I/O configured as inputs. If GPIO[7:4] are programmed
as modem pins, their interrupt generation must be enabled via IER register bit 3. In this
case bit 7 to bit 4 of IOIntEna will have no effect on GPIO[7:4].
Table 26.
Bit
7
6:0
Receiver FIFO Level register bits description
Symbol
Description
-
not used; set to zeros
RXLVL[6:0]
number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40)
Table 27.
Bit
7:0
IODir register bits description
Symbol
IODir
Description
set GPIO pins [7:0] to input or output
0 = input
1 = output
Table 28.
Bit
7:0
IOState register bits description
Symbol
Description
IOState
Write this register:
set the logic level on the output pins
0 = set output pin to zero
1 = set output pin to one
Read this register:
return states of all pins
Table 29.
Bit
7:0
IOIntEna register bits description
Symbol
Description
IOIntEna
input interrupt enable
0 = a change in the input pin will not generate an interrupt
1 = a change in the input will generate an interrupt
相關(guān)PDF資料
PDF描述
SC16IS750IPW Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS760IBS Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS760IPW Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS741IPW Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS752IBS Dual UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
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