參數(shù)資料
型號(hào): SC16IS750IBS
廠商: NXP Semiconductors N.V.
元件分類: 連接器件
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁(yè)數(shù): 14/62頁(yè)
文件大?。?/td> 308K
代理商: SC16IS750IBS
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
14 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
7.4 Hardware reset, Power-On Reset (POR) and software reset
These three reset methods are identical and will reset the internal registers as indicated in
Table 4
.
Table 4
summarizes the state of register.
[1]
Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal
RESET, POR or Software Reset, that is, they hold their initialization values during reset.
[2]
This register is not supported in SC16IS740.
[3]
Only UART Software Reset bit is supported in this register.
Table 5
summarizes the state of registers after reset.
Table 4.
Register
Interrupt Enable Register
Register reset
[1]
Reset state
all bits cleared
Interrupt Identification Register
FIFO Control Register
bit 0 is set; all other bits cleared
all bits cleared
Line Control Register
Modem Control Register
reset to 0001 1101 (0x1D)
all bits cleared
Line Status Register
Modem Status Register
bit 5 and bit 6 set; all other bits cleared
bits 0:3 cleared; bits 4:7 input signals
Enhanced Feature Register
Receiver Holding Register
all bits cleared
pointer logic cleared
Transmitter Holding Register
pointer logic cleared
Transmission Control Register
Trigger Level Register
all bits cleared.
all bits cleared.
Transmit FIFO level
reset to 0100 0000 (0x40)
Receive FIFO level
all bits cleared
I/O direction
[2]
all bits cleared
I/O interrupt enable
[2]
all bits cleared
I/O control
[3]
all bits cleared
Extra Feature Register
all bits cleared
Table 5.
Signal
TX
RTS
I/Os
IRQ
Output signals after reset
Reset state
HIGH
HIGH
inputs
HIGH by external pull-up
相關(guān)PDF資料
PDF描述
SC16IS750IPW Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS760IBS Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS760IPW Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS741IPW Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS752IBS Dual UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
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