參數(shù)資料
型號(hào): SC16IS750IBS
廠商: NXP Semiconductors N.V.
元件分類(lèi): 連接器件
英文描述: Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封裝: SC16IS740IPW/Q900<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.html<1<Always Pb-free,;SC16IS740IPW<SOT403-1 (TSSOP16)|<<http://www.nxp.com/packages/SOT403-1.
文件頁(yè)數(shù): 28/62頁(yè)
文件大?。?/td> 308K
代理商: SC16IS750IBS
SC16IS740_750_760_6
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 13 May 2008
28 of 62
NXP Semiconductors
SC16IS740/750/760
Single UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.7 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the
modem, data set, or peripheral device to the host. It also indicates when a control input
from the modem changes state.
Table 18
shows Modem Status Register bit settings.
[1]
Only available on SC16IS750/SC16IS760.
Remark:
The primary inputs RI, CD, CTS, DSR are all active LOW.
Table 18.
Bit
7
Modem Status Register bits description
Symbol
Description
MSR[7]
CD
[1]
(active HIGH, logical 1). If GPIO6 is selected as CD modem pin
through IOControl register bit 1, the state of CD pin can be read from this
bit. This bit is the complement of the CD input. Reading IOState bit 6 does
not reflect the true state of CD pin.
MSR[6]
RI
[1]
(active HIGH, logical 1). If GPIO7 is selected as RI modem pin through
IOControl register bit 1, the state of RI pin can be read from this bit. This bit
is the complement of the RI input. Reading IOState bit 6 does not reflect the
true state of RI pin.
MSR[5]
DSR
[1]
(active HIGH, logical 1). If GPIO4 is selected as DSR modem pin
through IOControl register bit 1, the state of DSR pin can be read from this
bit. This bit is the complement of the DSR input. Reading IOState bit 4 does
not reflect the true state of DSR pin.
MSR[4]
CTS (active HIGH, logical 1). This bit is the complement of the CTS input.
MSR[3]
CD
[1]
. Indicates that CD input has changed state. Cleared on a read.
MSR[2]
RI
[1]
. Indicates that RI input has changed state from LOW to HIGH.
Cleared on a read.
MSR[1]
DSR
[1]
. Indicates that DSR input has changed state. Cleared on a read.
MSR[0]
CTS. Indicates that CTS input has changed state. Cleared on a read.
6
5
4
3
2
1
0
相關(guān)PDF資料
PDF描述
SC16IS750IPW Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS760IBS Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS760IPW Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS741IPW Single UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
SC16IS752IBS Dual UART with I2C-bus-SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support
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