參數(shù)資料
型號(hào): SC16C852LIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
封裝: SC16C852LIB<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C852LIB<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1
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代理商: SC16C852LIBS
SC16C852L
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 4 — 1 February 2011
32 of 64
NXP Semiconductors
SC16C852L
1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 21.
Bit
7
Modem Control Register bits description
Symbol
Description
MCR[7]
Clock select
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
MCR[6]
IR enable (see
Figure 31
).
logic 0 = enable the standard modem receive and transmit input/output
interface (normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While
in this mode, the TX/RX output/inputs are routed to the infrared
encoder/decoder. The data input and output levels will conform to the
IrDA infrared interface requirement. As such, while in this mode, the
infrared TX output will be a logic 0 during idle data conditions.
MCR[5]
Reserved; set to ‘0’.
MCR[4]
Loopback. Enable the local loopback mode (diagnostics). In this mode the
transmitter output (TXA/TXB) and the receiver input (RXA/RXB), CTS, DSR,
CD, and RI are disconnected from the SC16C852L I/O pins. Internally the
modem data and control pins are connected into a loopback data
configuration (see
Figure 10
). In this mode, the receiver and transmitter
interrupts remain fully operational. The Modem Control Interrupts are also
operational, but the interrupts’ sources are switched to the lower four bits of
the Modem Control. Interrupts continue to be controlled by the IER register.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics)
MCR[3]
OP2A/OP2B, INT enable
logic 0 = forces INTA/INTB outputs to the 3-state mode and sets
OP2A/OP2B to a logic 1 (normal default condition)
logic 1 = forces the INTA/INTB outputs to the active mode and sets
OP2A/OP2B to a logic 0
Remark:
OP2A/OP2B pins do not exist on the HVQFN32 package.
MCR[2]
OP1A/OP1B are not available as an external signal in the SC16C852L. This
bit is instead used in the Loopback mode only. In the Loopback mode, this
bit is used to write the state of the modem RI interface signal.
MCR[1]
RTS
logic 0 = force RTSx output to a logic 1 (normal default condition)
logic 1 = force RTSx output to a logic 0
MCR[0]
DTR
logic 0 = force DTRx output to a logic 1 (normal default condition)
logic 1 = force DTRx output to a logic 0
6
5
4
3
2
1
0
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