參數(shù)資料
型號(hào): SC16C852LIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 1.8 V dual UART, 5 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA) and 16 mode or 68 mode bus interface
封裝: SC16C852LIB<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C852LIB<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1
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文件大?。?/td> 1160K
代理商: SC16C852LIBS
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SC16C852L internal registers
…continued
A2 A1 A0 Register
Default
[1]
Bit 7
Bit 6
Bit 5
S
A
P
R
2
N
S
1
[1]
The value shown represents the register’s initialized hexadecimal value; X = not applicable.
[2]
Accessible only when LCR[7] is logic 0, and EFCR[2:1] are logic 0.
[3]
This bit is only accessible when EFR[4] is set.
[4]
Baud rate registers accessible only when LCR[7] is logic 1.
[5]
Enhanced feature register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to 0xBF, and EFCR[2:1] are logic 0.
[6]
Second special registers are accessible only when EFCR[0] = 1, and EFCR[2:1] are logic 0.
[7]
First extra feature register set is only accessible when EFCR[2:1] = 01b.
[8]
Second extra feature register set is only accessible when EFCR[2:1] = 10b.
Enhanced feature register set
[5]
0
1
0
EFR
00
Auto CTS
Auto RTS
special
character
select
Enable
IER[7:4],
ISR[5:4],
FCR[5:4],
MCR[7:5]
bit 4
bit 12
bit 4
bit 12
Cont-3 TX,
RX Control
Cont-2 TX,
RX Control
Cont-1 TX,
RX Control
Cont-0 TX,
RX Control
R/W
1
1
1
1
First extra feature register set
[7]
0
1
0
TXINTLVL
1
0
0
RXINTLVL
1
1
0
FLWCNTH
1
1
1
FLWCNTL
Second extra feature register set
[8]
0
1
0
CLKPRES
1
0
0
RS485TIME 0x00
1
1
0
AFCR2
0
0
1
1
0
1
0
1
Xon1
Xon2
Xoff1
Xoff2
00
00
00
00
bit 7
bit 15
bit 7
bit 15
bit 6
bit 14
bit 6
bit 14
bit 5
bit 13
bit 5
bit 13
bit 3
bit 11
bit 3
bit 11
bit 2
bit 10
bit 2
bit 10
bit 1
bit 9
bit 1
bit 9
bit 0
bit 8
bit 0
bit 8
R/W
R/W
R/W
R/W
0x00
0x00
0x00
0x00
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
bit 6
bit 6
bit 5
bit 5
bit 5
bit 5
bit 4
bit 4
bit 4
bit 4
bit 3
bit 3
bit 3
bit 3
bit 2
bit 2
bit 2
bit 2
bit 1
bit 1
bit 1
bit 1
bit 0
bit 0
bit 0
bit 0
R/W
R/W
R/W
R/W
reserved
bit 7
reserved
reserved
bit 6
reserved
reserved
bit 5
RS485 RTS
Invert
reserved
reserved
bit 4
Auto RS485
RTS
Sleep
RXLow
bit 3
bit 3
RS485
RTS/DTR
reserved
bit 2
bit 2
Transmitter
Disable
RTS/CTS
mapped to
DTR/DSR
bit 1
bit 1
Receiver
Disable
Software
Reset
bit 0
bit 0
9-bit Enable
R/W
R/W
R/W
0x00
1
1
1
AFCR1
0x00
Concurrent
Write
reserved
TSR
Interrupt
R/W
Table 10.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
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